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| this is information on a product in full production. august 2013 docid15056 rev 5 1/80 stm32f102x8 stm32f102xb medium-density usb access lin e, arm-based 32b mcu with 64/128kb flash, usb fs, 6 timers, adc & 8 com. interfaces datasheet - production data features ? core: arm 32-bit cortex?-m3 cpu ? 48 mhz maximum frequency, 1.25 dmips/mhz (dhrystone 2.1) performance at 0 ws memory access ? single-cycle multiplic ation and hardware division ? memories ? 64 or 128 kbytes of flash memory ? 10 or 16 kbytes of sram ? clock, reset and supply management ? 2.0 to 3.6 v application supply and i/os ? por, pdr and programmable voltage detector (pvd) ? 4-to-16 mhz cr ystal oscillator ? internal 8 mhz factory-trimmed rc ? internal 40 khz rc ? pll for cpu clock ? 32 khz oscillator for rtc with calibration ? low power ? sleep, stop and standby modes ?v bat supply for rtc and backup registers ? debug mode ? serial wire debug (swd) and jtag interfaces ? dma ? 7-channel dma controller ? peripherals supported: timers, adc, spis, i 2 cs and usarts ? 1 12-bit, 1.2 s a/d converter (up to 16 channels) ? conversion range: 0 to 3.6 v ? temperature sensor ? up to 51 fast i/o ports ? 37/51 i/os all mappable on 16 external interrupt vectors and almost all 5 v-tolerant ? up to 6 timers ? three 16-bit timers, each with up to 4 ic/oc/pwm or pulse counter ? 2 watchdog timers (independent and window) ? systick timer: 24-bit downcounter ? up to 8 communication interfaces ? up to 2 x i 2 c interfaces (smbus/pmbus) ? up to 3 usarts (iso 7816 interface, lin, irda capability, modem control) ? up to 2 spis (12 mbit/s) ? one usb 2.0 full speed interface ? crc calculation unit, 96-bit unique id ? ecopack ? packages table 1. device summary reference part number stm32f102x8 stm32f102c8, stm32f102r8 stm32f102xb stm32f102cb, stm32f102rb lqfp48 7 7 mm lqfp64 10 10 mm www.st.com
contents stm32f102x8, stm32f102xb 2/80 docid15056 rev 5 contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.3 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3 pinout and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4 memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.1.1 minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.1.2 typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.1.3 typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.1.4 loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.1.5 pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.1.6 power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.1.7 current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.3.1 general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.3.2 operating conditions at power-up / powe r-down . . . . . . . . . . . . . . . . . . 31 5.3.3 embedded reset and power control bloc k characteristics . . . . . . . . . . . 32 5.3.4 embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.3.5 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.3.6 external clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.3.7 internal clock source charac teristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 5.3.8 pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5.3.9 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 5.3.10 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5.3.11 absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 50 5.3.12 i/o current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 docid15056 rev 5 3/80 stm32f102x8, stm32f102xb contents 3 5.3.13 i/o port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5.3.14 nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 5.3.15 tim timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 5.3.16 communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 5.3.17 12-bit adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 5.3.18 temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 6.1 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 6.2 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 6.3 reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 6.3.1 evaluating the maximum junction temperature for an application . . . . . 75 7 ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 8 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 list of tables stm32f102x8, stm32f102xb 4/80 docid15056 rev 5 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. stm32f102x8 and stm32f102xb medium-density usb access line features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 3. stm32f102xx usb access line family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 4. medium-density stm32f102xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 5. voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 6. current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 7. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 8. general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 9. operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 10. embedded reset and power control block characterist ics. . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 11. embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 table 12. maximum current consumption in run mode, code with data processing running from flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 13. maximum current consumption in run mode, code with data processing running from ram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 14. maximum current consumption in sleep mode, code running from flash or ram. . . . . . . 36 table 15. typical and maximum current consumptions in stop and standby modes . . . . . . . . . . . . 36 table 16. typical current consumption in run mode, code with data processing running from flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 17. typical current consumption in sleep mode, code running from flash or ram . . . . . . . . . 40 table 18. peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 19. high-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 20. low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 21. hse 4-16 mhz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 table 22. lse oscillator characteristics (f lse = 32.768 khz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 23. hsi oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 24. lsi oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 25. low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 26. pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 27. flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 28. flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 29. ems characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 30. emi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 31. esd absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 32. electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 33. i/o current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 34. i/o static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 35. output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 36. i/o ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 37. nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 38. timx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 39. i 2 c characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 40. scl frequency (f pclk1 = 36 mhz, v dd_i2c = 3.3 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 41. spi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 42. usb startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 43. usb dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 44. usb: full speed electrical characteristics of the driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 docid15056 rev 5 5/80 stm32f102x8, stm32f102xb list of tables 5 table 45. adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 46. r ain max for f adc = 12 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 47. adc accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 48. adc accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 49. ts characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 50. lqfp64 ? 10 x 10 mm, 64-pin low-profile quad flat package mechanical data . . . . . . . . . 71 table 51. lqfp48 ? 7 x 7 mm, 48-pin low-profile quad flat package mechanical data . . . . . . . . . . . 73 table 52. package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 53. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 54. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 list of figures stm32f102x8, stm32f102xb 6/80 docid15056 rev 5 list of figures figure 1. stm32f102t8 medium-density usb access line bloc k diagram . . . . . . . . . . . . . . . . . . . . 10 figure 2. clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 3. stm32f102xx medium-density usb access line lq fp48 pinout . . . . . . . . . . . . . . . . . . . 19 figure 4. stm32f102xx medium-density usb access line lq fp64 pinout . . . . . . . . . . . . . . . . . . . 19 figure 5. memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 6. pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 7. pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 8. power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 9. current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 10. typical current consumption in run mode versus temperature (at 3.6 v) - code with data processing running from ram, perip herals enabled. . . . . . . . . . . . . . . . . . 35 figure 11. typical current consumption in run mode versus temperature (at 3.6 v) - code with data processing running from ram, perip herals disabled . . . . . . . . . . . . . . . . . 35 figure 12. typical current consumption on v bat with rtc on versus temperature at different v bat values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 13. typical current consumption in stop mode with regulator in run mode versus temperature at v dd = 3.3 v and 3.6 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 14. typical current consumption in stop mode with regulator in low-power mode versus temperature at v dd = 3.3 v and 3.6 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 15. typical current consumption in standby mode versus temperature at v dd = 3.3 v and 3.6 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 16. high-speed external clock source ac timing diagra m . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 17. low-speed external clock source ac timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 18. typical application with an 8 mhz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 19. typical application with a 32.768 khz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 20. standard i/o input characterist ics - cmos port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 21. standard i/o input characteristics - ttl port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 figure 22. 5 v tolerant i/o inpu t characteristics - cmos port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 23. 5 v tolerant i/o input characteristics - ttl port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 24. i/o ac characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 25. recommended nrst pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 26. i 2 c bus ac waveforms and measurement circuit (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 27. spi timing diagram - slave mode and cpha=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 28. spi timing diagram - slave mode and cpha=1 (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 29. spi timing diagram - master mode (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 30. usb timings: definition of data signal rise and fa ll time . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 figure 31. adc accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 32. typical connection diagram using the adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 33. power supply and reference decoupling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 figure 34. lqfp64 ? 10 x 10 mm, 48-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . 70 figure 35. lqfp64 recommended footprint dimensions (1)(2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 36. lqfp48 ? 7 x 7 mm, 48-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . 72 figure 37. lqfp48 recommended footprint dimensions (1)(2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 figure 38. lqfp64 p d max vs. t a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 docid15056 rev 5 7/80 stm32f102x8, stm32f102xb introduction 79 1 introduction this datasheet provides the ordering informat ion and mechanical devic e characteristics of stm32f102x8 and stm32f102xb medium-densit y usb access line microcontrollers. for more details on the whole stmicroelectronics stm32f102xx family, please refer to section 2.2: full compatibilit y throughout the family . the medium-density stm32f102xx datasheet should be read in conjunction with the low-, medium- and high-density stm32f10xxx reference manual. for information on programming, erasing and protection of the internal flash memory please refer to the stm32f10xxx flash programming manual. the reference and flash programming manuals are both available from the stmicroelectronics website www.st.com. for information on the cortex?-m3 core please refer to the cortex?-m3 technical reference manual, available from the www. arm.com website at the following address: http://infocenter.arm.com/help/inde x.jsp?topic=/com.arm.doc.ddi0337e/. description stm32f102x8, stm32f102xb 8/80 docid15056 rev 5 2 description the stm32f102xx medium-density usb access line incorporates the high-performance arm cortex?-m3 32-bit risc core operat ing at a 48 mhz frequency, high-speed embedded memories (flash memory of 64 or 128 kbytes and sram of 10 or 16 kbytes), and an extensive ra nge of enhanced periphera ls and i/os connected to two apb buses. all devices offer standard communication interfaces (two i 2 cs, two spis, one usb and three usarts), one 12-bit adc and three general-purpose 16-bit timers. the stm32f102xx family operates in the ?40 to +85 c temperature range, from a 2.0 to 3.6 v power supply. a comprehensive set of power-saving mode allows the design of low- power applications. the stm32f102xx medium-density usb access line is delivered in the lqfp48 7 7 mm and lqfp64 10 10 mm packages. the stm32f102xx medium-density usb access line microcontrollers are suitable for a wide range of applications. ? application control and user interface ? medical and handheld equipment ? pc peripherals, gaming and gps platforms ? industrial applications: plc, in verters, printers, and scanners ? alarm systems, video intercom, and hvac figure 1 shows the general block diagram of the device family. docid15056 rev 5 9/80 stm32f102x8, stm32f102xb description 79 2.1 device overview table 2. stm32f102x8 and stm32f102xb medium-density usb access line features and peripheral counts peripheral stm32f102cx stm32f102rx flash - kbytes 64 128 64 128 sram - kbytes 10 16 10 16 timers general-purpose 33 3 3 communication interfaces spi 22 2 2 i 2 c 22 2 2 usart 33 3 3 usb 11 1 1 12-bit synchronized adc number of channels 1 10 channels 1 16 channels gpios 37 51 cpu frequency 48 mhz operating voltage 2.0 to 3.6 v operating temperatures ambient temperature: ?40 to +85 c (see table 8 ) junction temperature: ?40 to +105 c (see ta ble 8 ) packages lqfp48 lqfp64 description stm32f102x8, stm32f102xb 10/80 docid15056 rev 5 figure 1. stm32f102t8 medium-density usb access line block diagram 1. af = alternate function on i/o port pin. 2. t a = ?40 c to +85 c (junction temperature up to 105 c). temp sen so r pa[15:1] exti w w d g nvic 12bit adc1 swd 16 af jtdi jtck/swclk jtms/swdio jntrst jtdo nrst v dd = 2 to 3.6v 51af pb[15:0] pc[15:0] ahb2 mosi,miso,sck,nss sram x16bit) wakeup gpioa gpiob gpioc f max : 48 mhz v ss scl,sda, smba i2c2 gp dma tim2 tim3 xtal osc 4-16 mhz xtal 32 khz osc_in osc_out osc32_out osc32_in pll & apb1: f max = 24 mhz pclk1 hclk clock managt pclk2 as af as af volt. reg. 3.3v to 1.8v power backup interface as af 16 kb rtc rc 8 mhz cortex m3 cpu usart1 usart2 spi2 7 channels backup reg scl,sda,smba i2c1 as af rx,tx, cts, rts, usart3 pd[2:0] gpiod ahb: f max =48 mhz 4 channels 4 channels fclk rc 40 khz stand by iwdg @vdd @vbat por / pdr supply @vdda vdda vssa @vdda v bat ck, smartcard as af rx,tx, cts, rts, smart card as af rx,tx, cts, rts, apb2 : f max = 48 mhz nvic spi1 mosi,miso, sck,nss as af if in terface @vdda supervision pvd rst int @vdd ahb2 apb2 apb1 awu tamper-rtc flash 128 kb busm atrix 64 bit interface ibus dbus pbus obl flash trace controller ont system tim4 4 channels ai14868f traceclk traced[0:3] as as sw/jtag tpiu trace/trig ck, smartcard as af usb 2.0 fs usbdp, usbdm as af docid15056 rev 5 11/80 stm32f102x8, stm32f102xb description 79 figure 2. clock tree 1. for the usb function to be available, both hse and pll must be enabled, with the usb clock output (usbclk) at 48 mhz. 2. to have an adc conversion time of 1.2 s, apb2 must be at 12 mhz, 24 mhz or 48 mhz. 3. the flash memory programming interface cl ock (flitfclk) is always the hsi clock. hse osc 4-16 mhz osc_in osc_out osc32_in osc32_out lse osc 32.768 khz lsi rc 40 khz hs i r c 8 mhz to independent watchdog (iwdg) pll x2, x3, x4 pllmul legend: mco clock output main pllxtpre /2 ..., x16 ahb prescaler /1, 2..512 /2 pllclk hsi hse apb1 prescaler /1, 2, 4, 8, 16 adc prescaler /2, 4, 6, 8 adcclk pclk1 hclk pllclk to ahb bus, core, memory and dma usbclk to usb interface to tim2, 3 and 4 usb prescaler /1, 1.5 to adc lse lsi hsi /128 /2 hsi hse peripherals to apb1 peripheral clock enable (13 bits) enable (3 bits) p eripheral clock apb2 prescaler /1, 2, 4, 8, 16 pclk2 peripherals to apb2 peripheral clock enable (11 bits) 48 mhz 48 mhz max 48 mhz 48 mhz max 24 mhz max to rtc pllsrc sw mco css to cortex system timer /8 clock enable (3 bits) sysclk max rtcclk rtcsel[1:0] timxclk iwdgclk sysclk fclk cortex free running clock tim2,3, 4 if (apb1 prescaler =1) x1 else x2 hse = high-speed external clock signal hsi = high-speed internal clock signal lsi = low-speed internal clock signal lse = low-speed external clock signal ai14994b to flash prog. if flitfclk description stm32f102x8, stm32f102xb 12/80 docid15056 rev 5 2.2 full compatibility throughout the family the stm32f102xx is a complete family whose members are fully pin-to-pin, software and feature compatible. in the reference manual, the stm32f102x4 and stm32f102x6 are referred to as low-density devices and the stm32f102x8 and stm32f102xb are referred to as medium-density devices. low-density devices are an extension of the st m32f102x8/b devices, th ey are specified in the stm32f102x4/6 datasheet. low-density de vices feature lower flash memory and ram capacities, a timer and a few communication interfaces less. the stm32f102x4 and stm32f102x6 are a dr op-in replacement for the stm32f102x8/b medium-density devices, allowing the user to try different memory densities and providing a greater degree of freedom during the development cycle. moreover the stm32f102xx family is fully compatible with all existing stm32f101xx access line and stm32f103xx performance line devices. 2.3 overview arm ? cortex?-m3 core with embedded flash and sram the arm cortex?-m3 processor is the latest generation of arm processors for embedded systems. it has been developed to provide a low-cost platform that meets the needs of mcu implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts. the arm cortex?-m3 32-bit risc processor features exceptional code-efficiency, delivering the high-performance expected from an arm core in the memory size usually associated with 8- and 16-bit devices. the stm32f102xx medium-density usb access line having an embedded arm core, is therefore compatible with all arm tools and software. embedded flash memory 64 or 128 kbytes of embedded flash is available for storing programs and data. table 3. stm32f102xx usb access line family pinout low-density stm32f102xx devices me dium-density stm32f102xx devices 16 kb flash 32 kb flash (1) 1. for orderable part numbers that do not show the a internal code after the temperature range code (6), the reference datasheet for electrical characteristics is that of the stm32f102x 8/b medium-density devices. 64 kb flash 128 kb flash 4 kb ram 6 kb ram 10 kb ram 16 kb ram 64 2 usarts, 2 16-bit timers 1 spi, 1 i 2 c, 1 adc, 1 usb 3 usarts, 3 16-bit timers 2 spis, 2 i2cs, 1 adc, 1 usb 48 36 - - 2 usarts, 3 16- bit timers 1 spi, 1 i2c, 1 adc, 1 usb - docid15056 rev 5 13/80 stm32f102x8, stm32f102xb description 79 crc (cyclic redundancy check) calculation unit the crc (cyclic redundancy check) calculation unit is used to get a crc code from a 32-bit data word and a fixed generator polynomial. among other applications, crc-based techniques are used to verify data transmission or storage integrity. in the scope of the en/iec 60335-1 standard, they offer a means of verifying the flash memory integrity. the crc calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at link- time and stored at a given memory location. embedded sram 10 or 16 kbytes of embedded sram accessed (read/write) at cpu clock speed with 0 wait states. nested vectored interrupt controller (nvic) the stm32f102xx medium-density usb access line embeds a nested vectored interrupt controller able to handle up to 36 maskable interrupt channels (not including the 16 interrupt lines of cortex?-m3) an d 16 priority levels. ? closely coupled nvic gives lo w latency interrupt processing ? interrupt entry vector table address passed directly to the core ? closely coupled nvic core interface ? allows early processing of interrupts ? processing of late arriving higher priority interrupts ? support for tail-chaining ? processor state automatically saved ? interrupt entry restored on interrupt exit with no instruction overhead this hardware block provides flexible interrupt management features with minimal interrupt latency. external interrupt/event controller (exti) the external interrupt/event controller consists of 19 edge detectors lines used to generate interrupt/event requests. each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. a pending register maintains the status of the interrupt requests. the exti can detect external line with pulse width lower than the internal apb2 clock period. up to 51 gp ios are connected to the 16 external interrupt lines. clocks and startup system clock selection is perf ormed on startup, however the internal rc 8 mhz oscillator is selected as default cpu clock on reset. an external 4-16 mhz clock can be selected, in which case it is monitored for fa ilure. if failure is detected, th e system automatically switches back to the internal rc oscillator. a software interrupt is genera ted if enabled. similarly, full interrupt management of the pll clock entry is available when necessary (for example on failure of an indirectly used extern al crystal, resona tor or oscillator). several prescalers allow the configuration of the ahb frequency, the high speed apb (apb2) and the low speed apb (apb1) domains. the maximum frequency of the ahb and the apb domains is 48 mhz. see figure 2 for details on the clock tree. description stm32f102x8, stm32f102xb 14/80 docid15056 rev 5 boot modes at startup, boot pins are used to select one of five boot options: ? boot from user flash ? boot from system memory ? boot from embedded sram the boot loader is located in system memory. it is used to reprogram the flash memory by using usart1. for further details please refer to an2606. power supply schemes ? v dd = 2.0 to 3.6 v: external power supply for i/os and the internal regulator. provided externally through v dd pins. ? v ssa , v dda = 2.0 to 3.6 v: external analog po wer supplies for adc, reset blocks, rcs and pll (minimum voltage to be applied to v dda is 2.4 v when the adc is used). v dda and v ssa must be connected to v dd and v ss , respectively. ? v bat = 1.8 to 3.6 v: powe r supply for rtc, external cl ock 32 khz oscillator and backup registers (through power switch) when v dd is not present. for more details on how to connect power pins, refer to figure 8: power supply scheme . power supply supervisor the device has an integrated power on reset (por)/power down reset (pdr) circuitry. it is always active, and ensures proper operation starting from/down to 2 v. the device remains in reset mode when v dd is below a specified threshold, v por/pdr , without the need for an external reset circuit. the device features an embedded programmable voltage detector (pvd) that monitors the v dd /v dda power supply and compares it to the v pvd threshold. an interrupt can be generated when v dd /v dda drops below the v pvd threshold and/or when v dd /v dda is higher than the v pvd threshold. the interrupt service routine can then generate a warning message and/or put the mcu into a safe state. the pvd is enabled by software. refer to table 11: embedded reset and power control block characteristics for the values of v por/pdr and v pvd . voltage regulator the regulator has three operation modes: main (mr), low power (lpr) and power down. ? mr is used in the nominal regulation mode (run) ? lpr is used in the stop mode ? power down is used in standby mode: the re gulator output is in high impedance: the kernel circuitry is powered do wn, inducing zero consumption (but the contents of the registers and sram are lost) this regulator is always enabled after reset. it is disabled in standby mode, providing high impedance output. docid15056 rev 5 15/80 stm32f102x8, stm32f102xb description 79 low-power modes the stm32f102xx medium-density usb access line supports three low-power modes to achieve the best compromise between low po wer consumption, short startup time and available wakeup sources: ? sleep mode in sleep mode, only the cpu is stopped. all peripherals continue to operate and can wake up the cpu when an interrupt/event occurs. ? stop mode the stop mode achieves the lowest power consumption while retaining the content of sram and registers. all clocks in the 1.8 v domain are stopped, the pll, the hsi rc and the hse crystal oscillators are disabled . the voltage regulator can also be put either in normal or in low power mode. the device can be woken up from stop mode by any of the exti line. the exti line source can be one of the 16 external lines, the pvd output or the rtc alarm. ? standby mode the standby mode is used to achieve the lowest power consumption. the internal voltage regulator is switched off so that the entire 1.8 v domain is powered off. the pll, the hsi rc and the hse crystal oscillato rs are also switched off. after entering standby mode, sram and registers content ar e lost except for registers in the backup domain and standby circuitry. the device exits standby mode when an external reset (nrst pin), a iwdg reset, a rising edge on the wkup pin, or an rtc alarm occurs. note: the rtc, the iwdg, and the corresponding clock sources are not stopped by entering stop or standby mode. dma the flexible 7-channel general-purpose dma is able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. the dma controller supports circular buffer management avoiding the ge neration of interrupts when the controller reaches the end of the buffer. each channel is connected to dedicated hardw are dma requests, with support for software trigger on each channel. configuration is made by software and transfer sizes between source and destination are independent. the dma can be used with the main peripherals: spi, i 2 c, usart, general purpose timers timx and adc. rtc (real-time clock) and backup registers the rtc and the backup registers are supplied through a switch that takes power either on v dd supply when present or through the v bat pin. the backup regi sters are ten 16-bit registers used to store 20 bytes of user application data when v dd power is not present. the real-time clock provides a set of continuously running counters which can be used with suitable software to provide a clock calendar function, and provides an alarm interrupt and a periodic interrupt. it is clocked by a 32.768 khz external crystal, resonator or oscillator, the internal low power rc oscillator or the high -speed external clock divided by 128. the internal low power rc has a typical frequency of 40 khz. the rtc can be calibrated using an external 512 hz output to compensate for any natural crystal deviation. the rtc features a 32-bit programmable counter for long term measurement using the compare description stm32f102x8, stm32f102xb 16/80 docid15056 rev 5 register to generate an alarm. a 20-bit pres caler is used for the time base clock and is by default configured to generate a time base of 1 second from a clock at 32.768 khz. independent watchdog the independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. it is clocked from an independent 40 khz internal rc and as it operates independently from the main clock, it can operate in stop and st andby modes. it can be used as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. it is hardware or software configurable through the option bytes. the counter can be frozen in debug mode. window watchdog the window watchdog is based on a 7-bit downcounter that can be set as free running. it can be used as a watchdog to reset the device when a problem occurs. it is clocked from the main clock. it has an early warning interrupt capab ility and the counter can be frozen in debug mode. systick timer this timer is dedicated for os, but could also be used as a standard down counter. it features: ? a 24-bit down counter ? autoreload capability ? maskable system interrupt generation when the counter reaches 0. ? programmable clock source general-purpose timers (timx) there are 3 synchronizable general-purpose timers embedded in the stm32f102xx medium-density usb access line devices. thes e timers are based on a 16-bit auto-reload up/down counter, a 16-bit prescaler and f eature 4 independent channels each for input capture, output compare, pwm or one-pulse mode output. this gives up to 12 input captures / output compares / pwms on the lqfp48 and lqfp64 packages. the general-purpose timers can work together via the timer link feature for synchronization or event chaining. their counter can be frozen in debug mode. any of the general-purpose timers can be used to generate pwm outputs. they all have independent dma request generation. these timers are capable of handling quadrat ure (incremental) encoder signals and the digital outputs from 1 to 3 hall-effect sensors. i 2 c bus two i2c bus interfaces can operate in mult i-master and slave modes. they can support standard and fast modes. they support dual slav e addressing (7-bit only) and both 7/10-bit addressing in master mode. a hardware crc generation/verification is embedded. they can be served by dma and they support sm bus 2.0/pm bus. docid15056 rev 5 17/80 stm32f102x8, stm32f102xb description 79 universal synchronous/asynchronous receiver transmitter (usart) the available usart interfaces communicate at up to 2.25 mbit/s. they provide hardware management of the cts and rts signals, support irda sir endec, are iso 7816 compliant and have lin master/slave capability. the usart interfaces can be served by the dma controller. serial peripheral interface (spi) two spis are able to communicate up to 12 mbit /s in slave and master modes in full-duplex and simplex communication modes. the 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. the hardware crc generation/verification supports basic sd card/mmc modes. both spis can be served by the dma controller. universal serial bus (usb) the stm32f102xx medium-density usb access line embeds an usb device peripheral compatible with the usb full-speed 12 mbs. th e usb interface implements a full-speed (12 mbit/s) function interface. it has software configurable endpoint setting and suspend/resume support. the dedicated 48 mhz clock is gener ated from the internal main pll (the clock source must use a hs e crystal oscillator). gpios (general-purpose inputs/outputs) each of the gpio pins can be configured by so ftware as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. most of the gpio pins are shared with digital or analog alternate functions. all gpios are high current capable. the i/os alternate function configuration c an be locked if needed following a specific sequence in order to avoid spurious writing to the i/os registers. adc (analog to digital converter) the 12-bit analog to digital converter has up to 16 external channels and performs conversions in single-shot or scan modes. in scan mode, automatic conversion is performed on a selected group of analog inputs. the adc can be served by the dma controller. an analog watchdog feature allows very precis e monitoring of the converted voltage of one, some or all selected channels. an interrupt is generated when the converted voltage is outside the programmed thresholds. temperature sensor the temperature sensor has to generate a a vo ltage that varies linearly with temperature. the conversion range is between 2 v < v dda < 3.6 v. the temperature sensor is internally connected to the adc_in16 input channel wh ich is used to convert the sensor output voltage into a digital value. serial wire jtag debug port (swj-dp) the arm swj-dp interface is embedded. and is a combined jtag and serial wire debug port that enables either a serial wire debug or a jtag probe to be connected to the target. description stm32f102x8, stm32f102xb 18/80 docid15056 rev 5 the jtag tms and tck pins are shared re spectively with swdio and swclk and a specific sequence on the tms pin is us ed to switch between jtag-dp and sw-dp. docid15056 rev 5 19/80 stm32f102x8, stm32f102xb pinout and pin description 79 3 pinout and pin description figure 3. stm32f102xx medium-density usb access line lqfp48 pinout figure 4. stm32f102xx medium-density usb access line lqfp64 pinout 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 48 47 46 45 lqfp48 pa 3 pa 4 pa 5 pa 6 pa 7 pb0 pb1 pb2 pb10 pb11 vss_1 vdd_1 vdd_2 vss_2 pa 1 3 pa 1 2 pa 1 1 pa 1 0 pa 9 pa 8 pb15 pb14 pb13 pb12 vbat pc14-osc32_in pc15-osc32_out pd0-osc_in pd1-osc_out nrst vssa vdda pa 0 - w k u p pa 1 pa 2 vdd_3 vss_3 pb9 pb8 boot0 pb7 pb6 pb5 pb4 pb3 pa 1 5 pa 1 4 ai14378d pc13-tamper-rtc 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 29 30 31 32 25 26 27 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 vbat pc14-osc32_in pc15-osc32_out pd0-osc_in pd1-osc_out nrst pc0 pc1 pc2 pc3 vssa vdda pa 0 - w k u p pa 1 pa 2 vdd_3 vss_3 pb9 pb8 boot0 pb7 pb6 pb5 pb4 pb3 pd2 pc12 pc11 pc10 pa 1 5 pa 1 4 vdd_2 vss_2 pa 1 3 pa 1 2 pa 1 1 pa 1 0 pa 9 pa 8 pc9 pc8 pc7 pc6 pb15 pb14 pb13 pb12 pa 3 vss_4 vdd_4 pa 4 pa 5 pa 6 pa 7 pc4 pc5 pb0 pb1 pb2 pb10 pb11 vss_1 vdd_1 lqfp64 ai14387c pc13-tamper-rtc pinout and pin description stm32f102x8, stm32f102xb 20/80 docid15056 rev 5 table 4. medium-density stm32f102xx pin definitions pins pin name type (1) i / o level (2) main function (3) (after reset) alternate functions (3) (4) lqfp48 lqfp64 default remap 11 v bat sv bat 2 2 pc13-tamper-rtc (5) i/o pc13 (6) tamper-rtc 3 3 pc14-osc32_in (5) i/o pc14 (6) osc32_in 4 4 pc15-osc32_out (5) i/o pc15 (6) osc32_out 5 5 osc_in i/o ft osc_in pd0 (7) 6 6 osc_out i/o ft osc_out pd1 (7) 7 7 nrst i/o nrst - 8 pc0 i/o pc0 adc_in10 - 9 pc1 i/o pc1 adc_in11 - 10 pc2 i/o pc2 adc_in12 - 11 pc3 i/o pc3 adc_in13 812 v ssa sv ssa 913 v dda sv dda 10 14 pa0-wkup i/o pa0 wkup/usart2_cts/ adc_in0/ tim2_ch1_etr (8) 11 15 pa1 i/o pa1 usart2_rts/ adc_in1/tim2_ch2 (8) 12 16 pa2 i/o pa2 usart2_tx/ adc_in2/tim2_ch3 (8) 13 17 pa3 i/o pa3 usart2_rx/ adc_in3/tim2_ch4 (8) -18 v ss_4 sv ss_4 -19 v dd_4 sv dd_4 14 20 pa4 i/o pa4 spi1_nss (8) /adc_in4 usart2_ck/ 15 21 pa5 i/o pa5 spi1_sck (8) /adc_in5 16 22 pa6 i/o pa6 spi1_miso (8) /adc_in6/ tim3_ch1 (8) 17 23 pa7 i/o pa7 spi1_mosi (8) /adc_in7/ tim3_ch2 (8) - 24 pc4 i/o pc4 adc_in14 docid15056 rev 5 21/80 stm32f102x8, stm32f102xb pinout and pin description 79 - 25 pc5 i/o pc5 adc_in15 18 26 pb0 i/o pb0 adc_in8/tim3_ch3 (8) 19 27 pb1 i/o pb1 adc_in9/tim3_ch4 (8) 20 28 pb2 i/o ft pb2/boot1 21 29 pb10 i/o ft pb10 i2c2_scl/ usart3_tx (8) tim2_ch3 22 30 pb11 i/o ft pb11 i2c2_sda/ usart3_rx (8) tim2_ch4 23 31 v ss_1 sv ss_1 24 32 v dd_1 sv dd_1 25 33 pb12 i/o ft pb12 spi2_nss / i2c2_smba/ usart3_ck (8) 26 34 pb13 i/o ft pb13 spi2_sck (8) / usart3_cts 27 35 pb14 i/o ft pb14 spi2_miso/ usart3_rts 28 36 pb15 i/o ft pb15 spi2_mosi - 37 pc6 i/o ft pc6 tim3_ch1 - 38 pc7 i/o ft pc7 tim3_ch2 - 39 pc8 i/o ft pc8 tim3_ch3 - 40 pc9 i/o ft pc9 tim3_ch4 29 41 pa8 i/o ft pa8 usart1_ck/mco 30 42 pa9 i/o ft pa9 usart1_tx (8) 31 43 pa10 i/o ft pa10 usart1_rx (8) 32 44 pa11 i/o ft pa11 usart1_cts/usb_dm 33 45 pa12 i/o ft pa12 usart1_rts/usb_dp 34 46 pa13 i/o ft jtms- swdio pa13 35 47 v ss_2 sv ss_2 36 48 v dd_2 sv dd_2 37 49 pa14 i/o ft jtck/swcl k pa14 table 4. medium-density stm32f102xx pin definitions (continued) pins pin name type (1) i / o level (2) main function (3) (after reset) alternate functions (3) (4) lqfp48 lqfp64 default remap pinout and pin description stm32f102x8, stm32f102xb 22/80 docid15056 rev 5 38 50 pa15 i/o ft jtdi tim2_ch1_etr / pa15 /spi1_nss - 51 pc10 i/o ft pc10 usart3_tx - 52 pc11 i/o ft pc11 usart3_rx - 53 pc12 i/o ft pc12 usart3_ck - 54 pd2 i/o ft pd2 tim3_etr 39 55 pb3 i/o ft jtdo tim2_ch2/ pb3/ traceswo/ spi1_sck 40 56 pb4 i/o ft jntrst tim3_ch1 / pb4 spi1_miso 41 57 pb5 i/o pb5 i2c1_smba tim3_ch2 / spi1_mosi 42 58 pb6 i/o ft pb6 i2c1_scl (8) / tim4_ch1 usart1_tx 43 59 pb7 i/o ft pb7 i2c1_sda (8) / tim4_ch2 usart1_rx 44 60 boot0 i boot0 45 61 pb8 i/o ft pb8 tim4_ch3 i2c1_scl 46 62 pb9 i/o ft pb9 tim4_ch4 i2c1_sda 47 63 v ss_3 sv ss_3 48 64 v dd_3 sv dd_3 1. i = input, o = output, s = supply. 2. ft= 5 v tolerant. 3. function availability depends on the chos en device. for devices having reduced peripheral counts, it is always the lower number of peripherals that is included. fo r example, if a device has only one spi, two usarts and two timers, they will be called spi1, usart1 & usart2 and tim2 & tim 3, respectively. refer to table 2 on page 9table 3 on page 12 . 4. if several peripherals share the same i/o pin, to avoid conflict between these al ternate functions only one peripheral should be enabled at a time through the peripheral clock enable bit (in the corresponding rcc peripheral clock enable register). 5. pc13, pc14 and pc15 are supplied through the power switch. si nce the switch only sinks a li mited amount of current (3 ma), the use of gpios pc13 to pc15 in output mode is limited: the speed should not exceed 2 mhz with a maximum load of 30 pf and these ios must not be used as a current source (e.g. to drive an led). 6. main function after the first backup domain power-up. later on, it depends on the contents of the backup registers even after reset (because these registers are not reset by the main reset). for details on how to manage these ios, refer to the battery backup domain and bkp register des cription sections in the stm32f102xx reference manual, available from the stmicroelectronics website: www.st.com. table 4. medium-density stm32f102xx pin definitions (continued) pins pin name type (1) i / o level (2) main function (3) (after reset) alternate functions (3) (4) lqfp48 lqfp64 default remap docid15056 rev 5 23/80 stm32f102x8, stm32f102xb pinout and pin description 79 7. the pins number 5 and 6 in the lqfp48 package are conf igured as osc_in/osc_out after reset, however the functionality of pd0 and pd1 can be remapped by software on these pins. for more details, refer to the alternate function i/o and debug configuration section in the stm32f10xxx reference manual. the use of pd0 and pd1 in output mode is limited as they can only be used at 50 mhz in output mode. 8. this alternate function can be remapped by software to some other port pins (if available on the used package). for more details, refer to the alternate function i/o and debug conf iguration section in the st m32f10xxx reference manual, available from the stmicroelec tronics website: www.st.com. memory mapping stm32f102x8, stm32f102xb 24/80 docid15056 rev 5 4 memory mapping the memory map is shown in figure 5 . docid15056 rev 5 25/80 stm32f102x8, stm32f102xb memory mapping 79 figure 5. memory map 1k apb memory space dma rtc wwdg iwdg spi2 usart2 usart3 adc1 usart1 spi1 1k 35k 1k 1k 2k 1k 1k 2k 1k 1k 1k 1k 1k 7k 1k 1k 1k 1k 3k 1k 1k 1k 1k 1k 1k 1k 1k 2k 1k 1k 1k i2c2 exti rcc 1k 1k 1k 1k 1k 1k 1k 1k 3k 1k 3k 1k 4k 0 1 2 3 4 5 6 7 peripherals sram reserved reserved option bytes reserved 0x4000 0000 0x4000 0400 0x4000 0800 0x4000 0c00 0x4000 2800 0x4000 2c00 0x4000 3000 0x4000 3400 0x4000 3800 0x4000 3c00 0x4000 4400 0x4000 4800 0x4000 4c00 0x4000 5400 0x4000 5800 0x4000 5c00 0x4000 6000 0x4000 6400 0x4000 6800 0x4000 6c00 0x4000 7000 0x4000 7400 0x4001 0000 0x4001 0400 0x4001 0800 0x4001 0c00 0x4001 1000 0x4001 1400 0x4001 1800 0x4001 1c00 0x4001 2400 0x4001 2800 0x4001 2c00 0x4001 3000 0x4001 3400 0x4001 3800 0x4001 3c00 0x4002 0000 0x4002 0400 0x4002 1000 0x4002 1400 0x4002 2000 0x4002 2400 0x4002 3000 0x4002 3400 0x6000 0000 0xe010 0000 0xffff ffff reserved reserved reserved crc reserved reserved flash interface reserved reserved reserved reserved reserved reserved reserved port d port c port b port a afio pwr bkp reserved reserved 512 byte usb sram usb registers i2c1 reserved reserved reserved reserved tim4 tim3 tim2 0xffff ffff 0xe010 0000 0xe000 0000 0xc000 0000 0xa000 0000 0x8000 0000 0x6000 0000 0x4000 0000 0x2000 0000 0x0000 0000 0x1fff ffff 0x1fff f80f 0x1fff f800 0x1fff f000 0x0801ffff 0x0800 0000 system memory flash memory cortex-m3 internal peripherals ai14971c 0x2000 3fff 0xe000 0000 cortex-m3 internal peripherals 0x0000 0000 aliased to flash or system memory depending on boot pins reserved electrical characteristics stm32f102x8, stm32f102xb 26/80 docid15056 rev 5 5 electrical characteristics 5.1 parameter conditions unless otherwise specified, all voltages are referred to v ss . 5.1.1 minimum and maximum values unless otherwise specified the minimum and ma ximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at t a = 25 c and t a = t a max (given by the selected temperature range). data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3 ). 5.1.2 typical values unless otherwise specified, typical data are based on t a = 25 c, v dd = 3.3 v (for the 2v v dd 3.6 v voltage range). they are given only as design guidelines and are not tested. typical adc accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean2 ) . 5.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 5.1.4 loading capacitor the loading conditions used for pin parameter measurement are shown in figure 6 . 5.1.5 pin input voltage the input voltage measurement on a pin of the device is described in figure 7 . docid15056 rev 5 27/80 stm32f102x8, stm32f102xb electrical characteristics 79 5.1.6 power supply scheme figure 8. power supply scheme caution: in figure 8 , the 4.7 f capacitor must be connected to v dd3 . figure 6. pin loading conditi ons figure 7. pin input voltage ai14972 c = 50 pf stm32f102 pin ai14973 stm32f102 pin v in ai14882c v dd 1/2/3/4 an alo g: rcs, pll, ... po wer swi tch v bat gp i/o s out in kernel logic (cpu, digital & memories) backup circuitry (osc32k,rtc, backup registers) wake-up logic 3 100 nf + 1 4.7 f 1.8-3.6 v regulator v ss 1/2/3/4 v dda v ssa adc level shifter io logic v dd 10 nf + 1 f v dd v ref+ v ref- electrical characteristics stm32f102x8, stm32f102xb 28/80 docid15056 rev 5 5.1.7 current consumption measurement figure 9. current consumption measurement scheme 5.2 absolute maximum ratings stresses above the absolute maximum ratings listed in table 5: voltage characteristics , table 6: current characteristics , and table 7: thermal characteristics may cause permanent damage to the device. these are stress ratings only and functional ope ration of the device at these conditions is not im plied. exposure to maximum rating conditions for extended periods may affect device reliability. ai14126 v bat v dd v dda i dd _v bat i dd table 5. voltage characteristics symbol ratings min max unit v dd ? v ss external main supply voltage (including v dda and v dd ) (1) 1. all main power (v dd , v dda ) and ground (v ss , v ssa ) pins must always be connected to the external power supply, in the permitted range. ?0.3 4.0 v v in (2) 2. v in maximum must always be respected. refer to table 6: current characteristics for the maximum allowed injected current values. input voltage on five volt tolerant pin v ss ? 0.3 v dd + 4.0 input voltage on any other pin v ss ? 0.3 4.0 | v ddx | variations between different v dd power pins 50 mv |v ssx ? v ss | variations between all the different ground pins 50 v esd(hbm) electrostatic discharge voltage (human body model) see section 5.3.11: absolute maximum ratings (electrical sensitivity) docid15056 rev 5 29/80 stm32f102x8, stm32f102xb electrical characteristics 79 table 6. current characteristics symbol ratings max. unit i vdd total current into v dd /v dda power lines (source) (1) 1. all main power (v dd , v dda ) and ground (v ss , v ssa ) pins must always be connected to the external power supply, in the permitted range. 150 ma i vss total current out of v ss ground lines (sink) (1) 150 i io output current sunk by any i/o and control pin 25 output current source by any i/os and control pin ? 25 i inj(pin) (2) 2. negative injection disturbs the analog performance of the device. see note: on page 66 . injected current five volt tolerant pins (3) 3. positive injection is not possible on thes e i/os. a negative injection is induced by v in docid15056 rev 5 31/80 stm32f102x8, stm32f102xb electrical characteristics 79 5.3.2 operating conditions at power-up / power-down subject to general operating conditions for t a . table 9. operating conditions at power-up / power-down symbol parameter conditions min max unit t vdd v dd rise time rate 0 s/v v dd fall time rate 20 electrical characteristics stm32f102x8, stm32f102xb 32/80 docid15056 rev 5 5.3.3 embedded reset and power control block characteristics the parameters given in table 11 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 8 . . 5.3.4 embedded reference voltage the parameters given in table 12 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 8 . table 10. embedded reset and power control block characteristics symbol parameter conditions min typ max unit v pvd programmable voltage detector level selection pls[2:0]=000 (rising edge) 2.1 2.18 2.26 v pls[2:0]=000 (falling edge) 2 2.08 2.16 v pls[2:0]=001 (rising edge) 2.19 2.28 2.37 v pls[2:0]=001 (falling edge) 2.09 2.18 2.27 v pls[2:0]=010 (rising edge) 2.28 2.38 2.48 v pls[2:0]=010 (falling edge) 2.18 2.28 2.38 v pls[2:0]=011 (rising edge) 2.38 2.48 2.58 v pls[2:0]=011 (falling edge) 2.28 2.38 2.48 v pls[2:0]=100 (rising edge) 2.47 2.58 2.69 v pls[2:0]=100 (falling edge) 2.37 2.48 2.59 v pls[2:0]=101 (rising edge) 2.57 2.68 2.79 v pls[2:0]=101 (falling edge) 2.47 2.58 2.69 v pls[2:0]=110 (rising edge) 2.66 2.78 2.9 v pls[2:0]=110 (falling edge) 2.56 2.68 2.8 v pls[2:0]=111 (rising edge) 2.76 2.88 3 v pls[2:0]=111 (falling edge) 2.66 2.78 2.9 v v pvdhyst (2) pvd hysteresis 100 mv v por/pdr power on/power down reset threshold falling edge 1.8 (1) 1. the product behavior is guaranteed by design down to the minimum v por/pdr value. 1.88 1.96 v rising edge 1.84 1.92 2.0 v v pdrhyst pdr hysteresis 40 mv t rsttempo (2) 2. guaranteed by design, not tested in production. reset temporization 1.5 2.5 4.5 ms docid15056 rev 5 33/80 stm32f102x8, stm32f102xb electrical characteristics 79 5.3.5 supply current characteristics the current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, i/o pi n loading, device software configuration, operating frequencies, i/o pin switching rate, program location in memory and executed binary code. the current consumption is measured as described in figure 9: current consumption measurement scheme . all run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to dhrystone 2.1 code. maximum current consumption the mcu is placed under the following conditions: ? all i/o pins are in input mode with a static value at v dd or v ss (no load) ? all peripherals are disabled except if it is explicitly mentioned ? the flash access time is adjusted to f hclk frequency (0 wait state from 0 to 24 mhz, 1 wait state from 24 to 48 mhz) ? prefetch in on (reminder: this bit must be set before clock setting and bus prescaling) ? when the peripherals are enabled f pclk1 = f hclk/2 , f pclk2 = f hclk the parameters given in table 13 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 8 . table 11. embedded internal reference voltage symbol parameter conditions min typ max unit v refint internal reference voltage ?40 c < t a < +85 c 1.16 1.20 1.24 v t s_vrefint (1) 1. shortest sampling time can be determined in the application by multiple iterations. adc sampling time when reading the internal reference voltage 5.1 17.1 (2) 2. guaranteed by design, not tested in production. s v rerint (2) internal referenc e voltage spread over the temperature range v dd = 3 v 10 mv 10 mv t coeff (2) temperature coefficient 100 ppm/ c electrical characteristics stm32f102x8, stm32f102xb 34/80 docid15056 rev 5 table 12. maximum current consumption in run mode, code with data processing running from flash symbol parameter conditions f hclk max (1) 1. based on characterization results, not tested in production. unit t a = 85 c i dd supply current in run mode external clock (2) , all peripherals enabled 2. external clock is 8 mhz and pll is on when f hclk > 8 mhz. 48 mhz 36.1 ma 36 mhz 28.6 24 mhz 19.9 16 mhz 14.7 8 mhz 8.6 external clock (2) , all peripherals disabled 48 mhz 24.4 36 mhz 19.8 24 mhz 13.9 16 mhz 10.7 8 mhz 6.8 table 13. maximum current consumption in run mode, code with data processing running from ram symbol parameter conditions f hclk max unit t a = 85 c (1) 1. based on characterization, tested in production at v dd max, f hclk max. i dd supply current in run mode external clock (2) , all peripherals enabled 2. external clock is 8 mhz and pll is on when f hclk > 8 mhz. 48 mhz 31.5 ma 36 mhz 24 24 mhz 17.5 16 mhz 12.5 8 mhz 7.5 external clock (2) all peripherals disabled 48 mhz 20.5 36 mhz 16 24 mhz 11.5 16 mhz 8.5 8 mhz 5.5 docid15056 rev 5 35/80 stm32f102x8, stm32f102xb electrical characteristics 79 figure 10. typical current consumption in run mode versus temperature (at 3.6 v) - code with data processing running from ram, peripherals enabled figure 11. typical current consumption in run mode versus temperature (at 3.6 v) - code with data processing running from ram, peripherals disabled 0 5 10 15 20 25 30 -40 0 25 70 85 temperature (c) consumption (ma) 48 mhz 36 mhz 16 mhz 8 mhz 0 2 4 6 8 10 12 14 16 18 20 ?40 0 25 70 85 temperature (c) consumption (ma) 48 mhz 36 mhz 16 mhz 8 mhz electrical characteristics stm32f102x8, stm32f102xb 36/80 docid15056 rev 5 table 14. maximum current consumption in sleep mode, code running from flash or ram symbol parameter conditions f hclk max (1) unit t a = 85 c i dd supply current in sleep mode external clock (2) all peripherals enabled 48 mhz 20 ma 36 mhz 15.5 24 mhz 11.5 16 mhz 8.5 8 mhz 5.5 external clock (2) , all peripherals disabled 48 mhz 6 36 mhz 5 24 mhz 4.5 16 mhz 4 8 mhz 3 1. based on characterization, tested in production at v dd max and f hclk max with peripherals enabled. 2. external clock is 8 mhz and pll is on when f hclk > 8 mhz. table 15. typical and maximum current consumptions in stop and standby modes symbol parameter conditions typ (1) max unit v dd / v bat = 2.4 v v dd /v bat = 3.3 v v dd /v bat = 2.0 v t a = 85 c i dd supply current in stop mode regulator in run mode, low-speed and high-speed internal rc oscillators and high-speed oscillator off (no independent watchdog) 23.5 24 - 200 a regulator in low power mode, low-speed and high-speed internal rc oscillators and high-speed oscillator off (no independent watchdog) 13.5 14 - 180 supply current in standby mode (2) low-speed internal rc oscillator and independent watchdog on 2.6 3.4 - - ma low-speed internal rc oscillator on, independent watchdog off 2.4 3.2 - - low-speed internal rc oscillator and independent watchdog off, low- speed oscillator and rtc off 1.7 2 - 4 i dd_vbat backup domain supply current low-speed oscillator and rtc on 1.1 1.4 0.9 1.9 (3) a 1. typical values are measured at t a = 25 c. docid15056 rev 5 37/80 stm32f102x8, stm32f102xb electrical characteristics 79 figure 12. typical current consumption on v bat with rtc on versus temperature at different v bat values figure 13. typical current consumption in stop mode with regulator in run mode versus temperature at v dd = 3.3 v and 3.6 v 2. to have the standby consumption with rtc on, add i dd_vbat (low-speed oscillator and rtc on) to i dd standby (when v dd is present the backup domain is powered by v dd supply). 3. based on characterization, not tested in production. 0 0.5 1 1.5 2 2.5 ?40 c 25 c 70 c 8 5 c 105 c temper a t u re (c) con su mption ( a ) 2 v 2.4 v 3 v 3 .6 v a i17 3 51 0 20 40 60 80 100 120 140 -45 25 70 90 temperature (c) consumption (a) 3.3 v 3.6 v electrical characteristics stm32f102x8, stm32f102xb 38/80 docid15056 rev 5 figure 14. typical current consumption in stop mode with regulator in low-power mode versus temperature at v dd = 3.3 v and 3.6 v figure 15. typical current consumption in standby mode versus temperature at v dd = 3.3 v and 3.6 v 0 20 40 60 80 100 120 140 -40 0 25 70 85 temperature (c) consumption (a) 3.3 v 3.6 v standby mode 0 0.5 1 1.5 2 2.5 3 -45 25 70 90 temperature (c) consumption (a) 3.3 v 3.6 v docid15056 rev 5 39/80 stm32f102x8, stm32f102xb electrical characteristics 79 typical current consumption the mcu is placed under the following conditions: ? all i/o pins are in input mode with a static value at v dd or v ss (no load) ? all peripherals are disabled except if it is explicitly mentioned ? the flash access time is adjusted to f hclk frequency (0 wait state from 0 to 24 mhz, 1 wait state from 24 to 48 mhz) ? prefetch is on (reminder: this bit must be set before clock setting and bus prescaling) ? when the peripherals are enabled f pclk1 = f hclk/4 , f pclk2 = f hclk/2 , f adcclk = f pclk2 /4 the parameters given in table 17 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 8 . table 16. typical current consumption in run mode, code with data processing running from flash symbol parameter conditions f hclk typ (1) 1. typical values are measures at t a = 25 c, v dd = 3.3 v. typ (1) unit all peripherals enabled (2) 2. add an additional power consumption of 0.8 ma per adc for the analog part. in applications, this consumption occurs only while the adc is on (adon bit is set in the adc_cr2 register). all peripherals disabled i dd supply current in run mode external clock (3) 48 mhz 24.2 18.6 ma 36 mhz 19 14.8 24 mhz 12.9 10.1 16 mhz 9.3 7.4 8 mhz 5.5 4.6 4 mhz 3.3 2.8 2 mhz 2.2 1.9 1 mhz 1.6 1.45 500 khz 1.3 1.25 125 khz 1.08 1.06 running on high speed internal rc (hsi), ahb prescaler used to reduce the frequency 48 mhz 23.5 17.9 36 mhz 18.3 14.1 24 mhz 12.2 9.5 16 mhz 8.5 6.8 8 mhz 4.9 4 4 mhz 2.7 2.2 2 mhz 1.6 1.4 1 mhz 1.02 0.9 500 khz 0.73 0.67 125 khz 0.5 0.48 electrical characteristics stm32f102x8, stm32f102xb 40/80 docid15056 rev 5 3. external clock is 8 mhz and pll is on when f hclk > 8 mhz. table 17. typical current consumption in sleep mode, code running from flash or ram symbol parameter conditions f hclk typ (1) 1. typical values are measures at t a = 25 c, v dd = 3.3 v. typ (1) unit all peripherals enabled (2) 2. add an additional power consumption of 0.8 ma per adc for the analog part. in applications, this consumption occurs only while the adc is on (adon bit is set in the adc_cr2 register). all peripherals disabled idd supply current in sleep mode external clock (3) 3. external clock is 8 mhz and pll is on when f hclk > 8 mhz. 48 mhz 9.9 3.9 ma 36 mhz 7.6 3.1 24 mhz 5.3 2.3 16 mhz 3.8 1.8 8 mhz 2.1 1.2 4 mhz 1.6 1.1 2 mhz 1.3 1 1 mhz 1.11 0.98 500 khz 1.04 0.96 125 khz 0.98 0.95 running on high speed internal rc (hsi), ahb prescaler used to reduce the frequency 48 mhz 9.3 3.3 36 mhz 7 2.5 24 mhz 4.8 1.8 16 mhz 3.2 1.2 8 mhz 1.6 0.6 4 mhz 1 0.5 2 mhz 0.72 0.47 1 mhz 0.56 0.44 500 khz 0.49 0.42 125 khz 0.43 0.41 docid15056 rev 5 41/80 stm32f102x8, stm32f102xb electrical characteristics 79 on-chip peripheral current consumption the current consumption of the on -chip peripherals is given in table 19 . the mcu is placed under the following conditions: ? all i/o pins are in input mode with a static value at v dd or v ss (no load) ? all peripherals are disabled unless otherwise mentioned ? the given value is calculated by measuring the current consumption ? with all peripherals clocked off ? with only one peripheral clocked on ? ambient operating temperature and v dd supply voltage conditions summarized in table 5 . table 18. peripheral current consumption peripheral typical consumption at 25 c (1) 1. f hclk = 48 mhz, f apb1 = f hclk/2 , f apb2 = f hclk , default prescaler value for each peripheral. unit apb1 tim2 0.90 ma tim3 0.86 tim4 0.88 spi2 0.26 usart2 0.45 usart3 0.43 usb 0.57 i2c1 0.24 i2c2 0.25 apb2 gpio a 0.45 gpio b 0.32 gpio c 0.49 gpio d 0.32 adc1 (2) 2. specific conditions for adc: f hclk = 48 mhz, f apb1 = f hclk /2, f apb2 = f hclk , f adcclk = f hclk /4, adon bit in the adc_cr2 register is set to 1. 1.51 spi1 0.21 usart1 0.72 electrical characteristics stm32f102x8, stm32f102xb 42/80 docid15056 rev 5 5.3.6 external clock source characteristics high-speed external user clock generated from an external source the characteristics given in table 20 result from tests performed using an high-speed external clock source, and under ambient temperature and supply voltage conditions summarized in table 8 . low-speed external user clock generated from an external source the characteristics given in table 21 result from tests performed using an low-speed external clock source, and under ambient temperature and supply voltage conditions summarized in table 8 . table 19. high-speed external user clock characteristics symbol parameter conditions min typ max unit f hse_ext user external clock source frequency (1) 1825mhz v hseh osc_in input pin high level voltage 0.7v dd v dd v v hsel osc_in input pin low level voltage v ss 0.3v dd t w(hse) t w(hse) osc_in high or low time (1) 5 ns t r(hse) t f(hse) osc_in rise or fall time (1) 20 c in(hse) osc_in input capacitance (1) 5pf ducy (hse) duty cycle 45 55 % i l osc_in input leakage current v ss v in v dd 1 a 1. guaranteed by design, not tested in production. table 20. low-speed external user clock characteristics symbol parameter conditions min typ max unit f lse_ext user external clock source frequency (1) 32.768 1000 khz v lseh osc32_in input pin high level voltage 0.7v dd v dd v v lsel osc32_in input pin low level voltage v ss 0.3v dd t w(lse) t w(lse) osc32_in high or low time (1) 450 ns t r(lse) t f(lse) osc32_in rise or fall time (1) 50 c in(lse) osc32_in input capacitance (1) 5pf ducy (lse) duty cycle 30 70 % i l osc32_in input leakage current v ss v in v dd 1 a 1. guaranteed by design, not tested in production. docid15056 rev 5 43/80 stm32f102x8, stm32f102xb electrical characteristics 79 figure 16. high-speed external clock source ac timing diagram figure 17. low-speed external clock source ac timing diagram ai14975b os c _i n stm32f102xx v hseh t f(hse) t w(hse) i l 90% 10% t hse t t r(hse) t w(hse) f hse_ext v hsel external clock source ai14976b osc32_in stm32f102xx v lseh t f(lse) t w(lse) i l 90% 10% t lse t t r(lse) t w(lse) f lse_ext v lsel external clock source electrical characteristics stm32f102x8, stm32f102xb 44/80 docid15056 rev 5 high-speed external clock generated from a crystal/ceramic resonator the high-speed external (hse) clock can be supplied with a 4 to 16 mhz crystal/ceramic resonator oscillator. all th e information given in this paragraph are based on characterization results obtained with typical external components specified in table 22 . in the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion an d startup stabilization time. refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequenc y, package, accuracy). for c l1 and c l2 , it is recommended to use high-quality external ceramic capacitors in the 5 pf to 25 pf range (typ.), designed for high- frequency applications, and selected to match the requirements of the crystal or resonator (see figure 18 ). c l1 and c l2 are usually the same size. the crystal manufacturer typically specifies a load capacitance which is the series combination of c l1 and c l2 . pcb and mcu pin capacitance must be included (10 pf can be used as a rough estimate of the comb ined pin and board capacitance) when sizing c l1 and c l2 . refer to the application note an28 67 ?oscillator design guide for st microcontrollers? available from the st website www.st.com. table 21. hse 4-16 mhz oscillator characteristics (1)(2) 1. resonator characteristics given by the crystal/ceramic resonator manufacturer. 2. based on characterization results, not tested in production. symbol parameter conditions min typ max unit f osc_in oscillator frequency 4 8 16 mhz r f feedback resistor 200 k c recommended load capacitance versus equivalent serial resistance of the crystal (r s ) (3) 3. the relatively low value of the rf resistor offers a good protection against issues resulting from use in a humid environment, due to the induced leakage and the bias condition change. however, it is recommended to take this point into account if the mcu is used in tough humidity conditions. r s = 30 30 pf i 2 hse driving current v dd = 3.3 v v in = v ss with 30 pf load 1ma g m oscillator transconductance startup 25 ma/v t su(hse) (4) 4. t su(hse) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 mhz oscillation is reached. this value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer startup time v dd is stabilized 2 ms docid15056 rev 5 45/80 stm32f102x8, stm32f102xb electrical characteristics 79 figure 18. typical application with an 8 mhz crystal 1. r ext value depends on the cr ystal characteristics. low-speed external clock generated from a crystal/ceramic resonator the low-speed external (lse) clock can be supplied with a 32.768 khz crystal/ceramic resonator oscillator. all th e information given in this paragraph are based on characterization results obtained with typical external components specified in table 23 . in the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion an d startup stabilization time. refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequenc y, package, accuracy). ai14977b osc_ou t osc_in f hse c l1 r f stm32f102xx 8 mh z resonator bias controlled gain r ext (1) c l2 resonator with integrated capacitors table 22. lse oscillator characteristics (f lse = 32.768 khz) symbol parameter conditions min typ max unit r f feedback resistor 5 m c (1) recommended load capacitance versus equivalent serial resistance of the crystal (r s ) r s = 30 k 15 pf i 2 lse driving current v dd = 3.3 v v in = v ss 1.4 a g m oscillator transconductance 5 a/v t su(lse) (2) startup time v dd is stabilized t a = 50 c 1.5 s t a = 25 c 2.5 t a = 10 c 4.0 t a = 0 c 6.0 t a = ?1 0c 10.0 t a = ?2 0c 17.0 t a = ?3 0c 32.0 t a = ?4 0c 60.0 1. refer to the note and caution paragraphs below the table, and to the application note an 2867 ?oscillator design guide for st microcontrollers?. 2. t su(lse) is the startup time measured from the moment it is enabled by software to a stabili zed 32.768 khz oscillation is reached. this value is measured for a standard crystal and can va ry significantly with the crys tal manufacturer, pcb layout and humidity. electrical characteristics stm32f102x8, stm32f102xb 46/80 docid15056 rev 5 note: for cl1 and cl2 it is recommended to use high-quality ceramic capacitors in the 5 pf to 15 pf range selected to match the requirements of the crystal or resonator. cl1 and cl2, are usually the same size. the crystal manufacturer typically specifies a load capacitance which is the series combination of cl1 and cl2. load capacitance cl has the following form ula: cl = cl1 x cl2 / (cl1 + cl2) + c stray where c stray is the pin capacitance and board or trac e pcb-related capacitance. typically, it is between 2 pf and 7 pf. caution: to avoid exceeding the maximum value of c l1 and cl2 (15 pf) it is strongly recommended to use a resonator with a load capacitance cl 7 pf. never use a resonator with a load capacitance of 12.5 pf. example: if you choose a resonato r with a load capacitance of cl = 6 pf, and cstray = 2 pf, then cl1 = cl2 = 8 pf. figure 19. typical applicati on with a 32.768 khz crystal 5.3.7 internal clock source characteristics the parameters given in table 24 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 8 . high-speed internal (hsi) rc oscillator ai14978b osc32_ou t osc32_in f lse c l1 r f stm32f102xx 32.768 kh z resonator bias controlled gain c l2 resonator with integrated capacitors table 23. hsi oscillator characteristics (1) 1. v dd = 3.3 v, t a = ?40 to 105 c unless otherwise specified. symbol parameter conditions min typ max unit f hsi frequency 8 mhz ducy (hsi) duty cycle 45 55 % acc hsi accuracy of the hsi oscillator user-trimmed with the rcc_cr register (2) 1 (3) % factory- calibrated (4)(5) t a = ?40 to 105 c ?2 2.5 % t a = ?10 to 85 c ?1.5 2.2 % t a = 0 to 70 c ?1.3 2 % t a = 25 c ?1.1 1.8 % t su(hsi) (4) hsi oscillator startup time 12s i dd(hsi) (4) hsi oscillator power consumption 80 100 a docid15056 rev 5 47/80 stm32f102x8, stm32f102xb electrical characteristics 79 low-speed internal (lsi) rc oscillator wakeup time from low-power mode the wakeup times given in table 26 is measured on a wakeup phase with a 8-mhz hsi rc oscillator. the clock source used to wake up the device depends from the curren t operating mode: ? stop or standby mode: the clo ck source is the rc oscillator ? sleep mode: the clock source is the clock that was set before entering sleep mode. all timings are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 8 . 5.3.8 pll characteristics the parameters given in table 27 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 8 . 2. refer to application note an2868 ?stm32f10xxx internal rc oscillator (hsi) calibr ation? available from the st website www.st.com. 3. guaranteed by design, not tested in production. 4. based on characterization, not tested in production. 5. the actual frequency of hsi oscillator may be impacted by a reflow, but does not drift out of the specified range. table 24. lsi oscillator characteristics (1) 1. v dd = 3 v, t a = ? 40 to 85 c unless otherwise specified. symbol parameter min (2) 2. based on characterization, not tested in production. typ max unit f lsi frequency 30 40 60 khz t su(lsi) (3) 3. guaranteed by design, not tested in production. lsi oscillator startup time 85 s i dd(lsi) (3) lsi oscillator power consumption 0.65 1.2 a table 25. low-power mode wakeup timings symbol parameter typ unit t wusleep (1) 1. the wakeup times are measured from the wakeup event to the point at which the user application code reads the first instruction. wakeup from sleep mode 1.8 s t wustop (1) wakeup from stop mode (regulator in run mode) 3.6 s wakeup from stop mode (regulator in low-power mode) 5.4 t wustdby (1) wakeup from standby mode 50 s electrical characteristics stm32f102x8, stm32f102xb 48/80 docid15056 rev 5 5.3.9 memory characteristics flash memory the characteristics are given at t a = ?40 to 85 c unless otherwise specified. table 26. pll characteristics symbol parameter value unit min (1) typ max (1) 1. based on characterization, not tested in production. f pll_in pll input clock (2) 2. take care of using the appropriate multiplier factors so as to have pll input clock values compatible with the range defined by f pll_out . 18.025mhz pll input clock duty cycle 40 60 % f pll_out pll multiplier output clock 16 48 mhz t lock pll lock time 200 s jitter cycle-to-cycle jitter 300 ps table 27. flash memory characteristics symbol parameter conditions min (1) 1. guaranteed by design, not tested in production. typ max (1) unit t prog 16-bit programming time t a = ?40 to +85 c 40 52.5 70 s t erase page (1 kb) erase time t a = ?40 to +85 c 20 40 ms t me mass erase time t a = ?40 to +85 c 20 40 ms i dd supply current read mode f hclk = 48 mhz with 2 wait states, v dd = 3.3 v 20 ma write / erase modes f hclk = 48 mhz, v dd = 3.3 v 5ma power-down mode / halt, v dd = 3.0 to 3.6 v 50 a v prog programming voltage 2 3.6 v table 28. flash memory endurance and data retention symbol parameter conditions value unit min (1) 1. based on characterization not tested in production. typ max n end endurance 10 kcycles t ret data retention t a = 85 c, 1000 cycles 30 years docid15056 rev 5 49/80 stm32f102x8, stm32f102xb electrical characteristics 79 5.3.10 emc characteristics susceptibility tests are perf ormed on a sample basis duri ng device characterization. functional ems (electromagnetic susceptibility) while a simple application is executed on t he device (toggling 2 leds through i/o ports). the device is stressed by two electromagnetic events until a failure o ccurs. the failure is indicated by the leds: ? electrostatic discharge (esd) (positive and negative) is applied to all device pins until a functional disturbance occurs. this test is compliant with the iec 61000-4-2 standard. ? ftb : a burst of fast transient voltage (positive and negative) is applied to v dd and v ss through a 100 pf capacitor, until a func tional disturbance occurs. this test is compliant with the iec 61000-4-4 standard. a device reset allows normal operations to be resumed. the test results are given in table 31 . they are based on the ems levels and classes defined in application note an1709. designing hardened software to avoid noise problems emc characterization and optimization are per formed at component level with a typical application environment and simplified mcu soft ware. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user applies emc software optimization and pre qualification tests in relation with the emc level requested for his application. software recommendations: the software flowchart must include the management of runaway conditions such as: ? corrupted program counter ? unexpected reset ? critical data corruption (control registers, etc.) prequalification trials most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forci ng a low state on the nrst pin or the oscillator pins for 1 second. to complete these trials, esd stress can be app lied directly on the device, over the range of specification values. when unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note an1015). table 29. ems characteristics symbol parameter conditions level/class v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance v dd = 3.3 v, t a = +25 c, f hclk = 48 mhz conforms to iec 61000-4-2 2b v eftb fast transient voltage burst limits to be applied through 100 pf on v dd and v ss pins to induce a functional disturbance v dd = 3.3 v, t a = +25 c, f hclk = 48 mhz conforms to iec 61000-4-4 4a electrical characteristics stm32f102x8, stm32f102xb 50/80 docid15056 rev 5 electromagnetic interference (emi) the electromagnetic field emitted by the device is monitored while a simple application is executed (toggling 2 leds through the i/o por ts). this emission test is compliant with iec 61967-2 standard which specifies the test board and the pin loading. 5.3.11 absolute maximum ratings (electrical sensitivity) based on three different tests (esd, lu) using specific measurement methods, the device is stressed in order to determ ine its performance in terms of electrical sensitivity. electrostatic discharge (esd) electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combinati on. the sample size depends on the number of supply pins in the device (3 parts (n+1) supply pins). this test conforms to the jesd22-a114/c101 standard. static latch-up two complementary static te sts are required on six pa rts to assess the latch-up performance: ? a supply overvoltage is applied to each power supply pin ? a current injection is applied to each input, output and configurable i/o pin these tests are compliant with eia/jesd 78 ic latch-up standard. table 30. emi characteristics symbol parameter conditions monitored frequency band max vs. [f hse /f hclk ] unit 8/48 mhz s emi peak level v dd = 3.3 v, t a = 25 c, 0.1 mhz to 30 mhz 7 dbv 30 mhz to 130 mhz 8 130 mhz to 1ghz 13 sae emi level 3.5 - table 31. esd absolute maximum ratings symbol ratings conditions class maximum value (1) 1. based on characterization results, not tested in production. unit v esd(hbm) electrostatic discharge voltage (human body model) t a = +25 c, conforming to jesd22-a114 2 2000 v v esd(cdm) electrostatic discharge voltage (charge device model) t a = +25 c, conforming to ansi/esd stm5.3.1 ii 500 table 32. electrical sensitivities symbol parameter conditions class lu static latch-up class t a = +105 c conforming to jesd78a ii level a docid15056 rev 5 51/80 stm32f102x8, stm32f102xb electrical characteristics 79 5.3.12 i/o current in jection characteristics as a general rule, current injection to the i/o pins, due to external voltage below v ss or above v dd (for standard, 3 v-capable i/o pins) should be avoided during normal product operation. however, in order to give an indica tion of the robustness of the microcontroller in cases when abnormal injection ac cidentally happens, susceptib ility tests are pe rformed on a sample basis during device characterization. functional susceptibilty to i/o current injection while a simple application is executed on the de vice, the device is stressed by injecting current into the i/o pins programmed in floating input mode . while current is injected into the i/o pin, one at a time, the device is checked for functional failures. the failure is indicated by an out of range parameter: adc error above a certain limit (>5 lsb tue), out of spec current injection on adja cent pins or other functional failure (for example reset, oscillator frequency deviation). the test results are given in table 35 . 5.3.13 i/o port characteristics general input/output characteristics unless otherwise specified, the parameters given in table 36 are derived from tests performed under the conditions summarized in table 8 . all i/os are cmos and ttl compliant. general input/output characteristics unless otherwise specified, the parameters given in table 34 are derived from tests performed under the conditions summarized in table 8 . all i/os are cmos and ttl compliant. table 33. i/o current injection susceptibility symbol description functional susceptibility unit negative injection positive injection i inj injected current on osc_in32, osc_out32, pa4, pa5, pc13 -0 +0 ma injected current on all ft pins -5 +0 injected current on any other pin -5 +5 electrical characteristics stm32f102x8, stm32f102xb 52/80 docid15056 rev 5 table 34. i/o static characteristics symbol parameter conditions min typ max unit v il low level input voltage standard io input low level voltage - - 0.28*(v dd -2 v)+0.8 v (1) v io ft (3) input low level voltage - - 0.32*(v dd -2v)+0.75 v (1) all i/os except boot0 - - 0.35v dd (2) v ih high level input voltage standard io input high level voltage 0.41*(v dd -2 v)+1.3 v (1) -- io ft (3) input high level voltage 0.42*(v dd -2 v)+1 v (1) -- all i/os except boot0 0.65v dd (2) -- v hys standard io schmitt trigger voltage hysteresis (4) 200 - - mv io ft schmitt trigger voltage hysteresis (4) 5% v dd (5) -- i lkg input leakage current (6) v ss v in v dd standard i/os -- 1 a v in = 5 v i/o ft --3 r pu weak pull-up equivalent resistor (7) v in = v ss 30 40 50 k r pd weak pull-down equivalent resistor (7) v in = v dd 30 40 50 c io i/o pin capacitance - 5 - pf 1. data based on design simulation. 2. tested in production. 3. ft = five-volt tolerant. in order to sustain a voltage higher than v dd +0.3 the internal pull-up/pull-down resistors must be disabled. 4. hysteresis voltage between schmitt trigger switching leve ls. based on characterization, not tested in production. 5. with a minimum of 100 mv. 6. leakage could be higher than max. if negativ e current is injected on adjacent pins. 7. pull-up and pull-down resistor s are designed with a true resistance in seri es with a switchable pmos/nmos. this pmos/nmos contribution to the series resistance is minimum (~10% order) . docid15056 rev 5 53/80 stm32f102x8, stm32f102xb electrical characteristics 79 all i/os are cmos and ttl compliant (no software configuration required). their characteristics cover more than the strict cmos-technology or ttl parameters. the coverage of these requirements is shown in figure 20 and figure 21 for standard i/os, and in figure 22 and figure 23 for 5 v tolerant i/os. figure 20. standard i/o input characteristics - cmos port figure 21. standard i/o input characteristics - ttl port ai17277c v dd (v) 1.3 0.8 2 3.6 2.7 3 0.7 cmos standard requirement v ih =0.65v dd 3.3 v ih /v il (v) 7 ilmax 7 ihmin tested in production v dd -2)+0.8 =0.28(v il cmos standard requirement v il =0.35v dd v ih =0.41(v dd -2)+1.3 tested in production based on design simulations based on design simulations area not determined ai17278b 2 3.6 v ih /v il (v) 1.3 2.0 0.8 2.16 ttl requirements v ih =2v v ih =0.41(v dd -2)+1.3 v il =0.28(v dd -2)+0.8 ttl requirements v il =0.8v 1.96 1.25 v dd (v) 7 ilmax 7 ihmin based on design simulations based on design simulations area not determined electrical characteristics stm32f102x8, stm32f102xb 54/80 docid15056 rev 5 figure 22. 5 v tolerant i/o inpu t characteristics - cmos port figure 23. 5 v tolerant i/o input characteristics - ttl port output driving current the gpios (general purpose input/outputs) can sink or source up to 8 ma, and sink or source up to 20 ma (with a relaxed v ol /v oh ) except pc13, pc14 and pc15 which can sink or source up to 3 ma. when using the gpios pc13 to pc15 in output mode, the speed should not exceed 2 mhz with a maximum load of 30 pf. in the user application, the number of i/o pi ns which can drive curr ent must be limited to respect the absolute maximum rating specified in section 5.2 : ? the sum of the currents sourced by all the i/os on v dd, plus the maximum run consumption of the mcu sourced on v dd, cannot exceed the absolute maximum rating i vdd (see table 6 ). ? the sum of the currents sunk by all the i/os on v ss plus the maximum run consumption of the mcu sunk on v ss cannot exceed the absolute maximum rating i vss (see table 6 ). vdd 1.3 2 3.6 cmos standard requirements v ih =0.65v dd cmos standard requirment v il =0.35v dd 1.67 1 2.7 0.7 33.3 1 0.75 1.295 0.975 1.42 1.07 1.55 1.16 v ih /v il (v) v dd (v) ai17279c v ih =0.42(v dd -2)+1 v il =0.32(v dd -2)+0.75 based on design simulations based on design simulations tested in production tested in production area not determined 2.0 0.8 2 3.6 2.16 1.67 1 0.75 ttl requirement v ih =2v ttl requirements v il =0.8v v ih /v il (v) v dd (v) 7 ilmax 7 ihmin ai17280b v ih =0.42*(v dd -2)+1 v il =0.32*(v dd -2)+0.75 based on design simulations based on design simulations area not determined docid15056 rev 5 55/80 stm32f102x8, stm32f102xb electrical characteristics 79 output voltage levels unless otherwise specified, the parameters given in table 37 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 8 . all i/os are cmos and ttl compliant. table 35. output voltage characteristics symbol parameter conditions min max unit v ol (1) 1. the i io current sunk by the device must always res pect the absolute maximum rating specified in table 6 and the sum of i io (i/o ports and control pins) must not exceed i vss . output low level voltage for an i/o pin when 8 pins are sunk at the same time cmos port (2) , i io = +8 ma, 2.7 v < v dd < 3.6 v 2. ttl and cmos outputs are compatible with jedec standards jesd36 and jesd52. 0.4 v v oh (3) 3. the i io current sourced by the device must always re spect the absolute maximum rating specified in table 6 and the sum of i io (i/o ports and control pins) must not exceed i vdd . output high level voltage for an i/o pin when 8 pins are sourced at the same time v dd ?0.4 v ol (1) output low level voltage for an i/o pin when 8 pins are sunk at the same time ttl port (2) i io = +8 ma 2.7 v < v dd < 3.6 v 0.4 v v oh (3) output high level voltage for an i/o pin when 8 pins are sourced at the same time 2.4 v ol (1) output low level voltage for an i/o pin when 8 pins are sunk at the same time i io = +20 ma (4) 2.7 v < v dd < 3.6 v 4. based on characterization data, not tested in production. 1.3 v v oh (3) output high level voltage for an i/o pin when 8 pins are sourced at the same time v dd ?1.3 v ol (1) output low level voltage for an i/o pin when 8 pins are sunk at the same time i io = +6 ma (4) 2 v < v dd < 2.7 v 0.4 v v oh (3) output high level voltage for an i/o pin when 8 pins are sourced at the same time v dd ?0.4 electrical characteristics stm32f102x8, stm32f102xb 56/80 docid15056 rev 5 input/output ac characteristics the definition and values of input/output ac characteristics are given in figure 24 and table 38 , respectively. unless otherwise specified, the parameters given in table 38 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 8 . table 36. i/o ac characteristics (1) 1. the i/o speed is configured using the modex[1:0] bits. refer to the stm32f10xxx reference manual for a description of gpio port configuration register. modex [1:0] bit value (1) symbol parameter conditions max unit 10 f max(io)out maximum frequency (2) 2. the maximum frequency is defined in figure 24 . c l = 50 pf, v dd = 2 v to 3.6 v 2 mhz t f(io)out output high to low level fall time c l = 50 pf, v dd = 2 v to 3.6 v 125 (3) 3. guaranteed by design, not tested in production. ns t r(io)out output low to hi gh level rise time 125 (3) 01 f max(io)out maximum frequency (2) c l = 50 pf, v dd = 2 v to 3.6 v 10 mhz t f(io)out output high to low level fall time c l = 50 pf, v dd = 2 v to 3.6 v 25 (3) ns t r(io)out output low to hi gh level rise time 25 (3) 11 f max(io)out maximum frequency (2) c l = 30 pf, v dd = 2.7 v to 3.6 v 50 mhz c l = 50 pf, v dd = 2.7 v to 3.6 v 30 mhz c l = 50 pf, v dd = 2 v to 2.7 v 20 mhz t f(io)out output high to low level fall time c l = 30 pf, v dd = 2.7 v to 3.6 v 5 (3) ns c l = 50 pf, v dd = 2.7 v to 3.6 v 8 (3) c l = 50 pf, v dd = 2 v to 2.7 v 12 (3) t r(io)out output low to hi gh level rise time c l = 30 pf, v dd = 2.7 v to 3.6 v 5 (3) c l = 50 pf, v dd = 2.7 v to 3.6 v 8 (3) c l = 50 pf, v dd = 2 v to 2.7 v 12 (3) -t extipw pulse width of external signals detected by the exti controller 10 ns docid15056 rev 5 57/80 stm32f102x8, stm32f102xb electrical characteristics 79 figure 24. i/o ac charac teristics definition 5.3.14 nrst pin characteristics the nrst pin input driver uses cmos technology. it is connected to a permanent pull-up resistor, r pu (see table 36 ). unless otherwise specified, the parameters given in table 39 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 8 . ai14131c 10% 90% 50% t r(io)out output external on 50pf maximum frequency is achieved if (t r + t f ) 2/3)t and if the duty cycle is (45-55%) 10% 50% 90% when loaded by 50pf t t f(io)out table 37. nrst pin characteristics symbol parameter conditions min typ max unit v il(nrst) (1) 1. guaranteed by design, not tested in production. nrst input low level voltage ?0.5 0.8 v v ih(nrst) (1) nrst input high level voltage 2 v dd +0.5 v hys(nrst) nrst schmitt trigger voltage hysteresis 200 mv r pu weak pull-up equivalent resistor (2) 2. the pull-up is designed with a true resistance in seri es with a switchable pmos. this pmos contribution to the series resistance must be minimum (~10% order) . v in = v ss 30 40 50 k v f(nrst) (1) nrst input filtered pulse 100 ns v nf(nrst) (1) nrst input not filtered pulse 300 ns electrical characteristics stm32f102x8, stm32f102xb 58/80 docid15056 rev 5 figure 25. recommended nrst pin protection 1. the reset network protects t he device against par asitic resets. 2. the user must ensure that the level on the nrst pin can go below the v il(nrst) max level specified in table 39 . otherwise the reset will not be taken into account by the device. ai14132c stm32fxxx r pu nrst (2) v dd filter internal reset 0.1 f external reset circuit (1) docid15056 rev 5 59/80 stm32f102x8, stm32f102xb electrical characteristics 79 5.3.15 tim time r characteristics the parameters given in table 40 are guaranteed by design. refer to section 5.3.13: i/o port characteristics for details on the input/output alternate function characteristics (output compare, i nput capture, external clock, pwm output). 5.3.16 communications interfaces i 2 c interface characteristics the stm32f102xx medium-density usb access line i 2 c interface meets the requirements of the standard i 2 c communication protocol with the following restrictions: t he i/o pins sda and scl are mapped to are not ?true? open-drain. when configured as open-drain, the pmos connected between the i/o pin and v dd is disabled, but is still present. the i 2 c characteristics are described in table 41 . refer also to section 5.3.13: i/o port characteristics for more details on the input/output al ternate function characteristics (sda and scl) . table 38. timx (1) characteristics 1. timx is used as a general term to re fer to the tim2, tim3 and tim4 timers. symbol parameter conditions min max unit t res(tim) timer resolution time 1t timxclk f timxclk = 48 mhz 20.84 ns f ext timer external clock frequency on ch1 to ch4 0f timxclk /2 mhz f timxclk = 48 mhz 0 24 mhz res tim timer resolution 16 bit t counter 16-bit counter clock period when internal clock is selected 1 65536 t timxclk f timxclk = 48 mhz 0.0208 1365 s t max_count maximum possible count 65536 65536 t timxclk f timxclk = 48 mhz 89.48 s electrical characteristics stm32f102x8, stm32f102xb 60/80 docid15056 rev 5 table 39. i 2 c characteristics symbol parameter standard mode i 2 c (1) 1. values guaranteed by design, not tested in production. fast mode i 2 c (1) (2) 2. f pclk1 must be at least 2 mhz to achieve standard mode i 2 c frequencies. it must be at least 4 mhz to achieve fast mode i 2 c frequencies. it must be a multiple of 10 mhz to reach the 400 khz maximum i2c fast mode clock. unit min max min max t w(scll) scl clock low time 4.7 1.3 s t w(sclh) scl clock high time 4.0 0.6 t su(sda) sda setup time 250 100 ns t h(sda) sda data hold time 0 (3) 3. the maximum data hold time has only to be met if the interface does not stretch the low period of the scl signal. 0 900 (3) t r(sda) t r(scl) sda and scl rise time 1000 20+0.1c b 300 t f(sda) t f(scl) sda and scl fall time 300 300 t h(sta) start condition hold time 4.0 0.6 s t su(sta) repeated start condition setup time 4.7 0.6 t su(sto) stop condition setup time 4.0 0.6 s t w(sto:sta) stop to start condition time (bus free) 4.7 1.3 s c b capacitive load for each bus line 400 400 pf docid15056 rev 5 61/80 stm32f102x8, stm32f102xb electrical characteristics 79 figure 26. i 2 c bus ac waveforms and measurement circuit (1) 1. measurement points are done at cmos levels: 0.3v dd and 0.7v dd. table 40. scl frequency (f pclk1 = 36 mhz, v dd_i2c = 3.3 v) (1)(2) 1. r p = external pull-up resistance, f scl = i 2 c speed, 2. for speeds around 200 khz, the tolerance on the achieved speed is of 5%. for other speed ranges, the tolerance on the achieved speed 2%. these variations depend on the accuracy of the external components used to design the application. f scl (khz) i2c_ccr value r p = 4.7 k 400 0x801e 300 0x8028 200 0x803c 100 0x00b4 50 0x0168 20 0x0384 ai14133e start sd a i2c bus v dd_i2c v dd_i2c stm32f10x sda scl t f(sda) t r(sda) scl t h(sta) t w(sclh) t w(scll) t su(sda) t r(scl) t f(scl) t h(sda) start repeated start t su(sta) t su(sto) stop t su(sto:sta) rp rp rs rs electrical characteristics stm32f102x8, stm32f102xb 62/80 docid15056 rev 5 spi interface characteristics unless otherwise specified, the parameters given in table 43 are derived from tests performed under ambient temperature, f pclkx frequency and v dd supply voltage conditions summarized in table 8 . refer to section 5.3.13: i/o port characteristics for more details on the input/output alternate function characteristics (nss, sck, mosi, miso). table 41. spi characteristics symbol parameter conditions min max unit f sck 1/t c(sck) spi clock frequency master mode 18 mhz slave mode 18 t r(sck) t f(sck) spi clock rise and fall time capacitive load: c = 30 pf 8 ns ducy(sck) spi slave input clock duty cycle slave mode 30 70 % t su(nss) (1) 1. based on characterization, not tested in production. nss setup time slave mode 4t pclk ns t h(nss) (1) nss hold time slave mode 2t pclk t w(sckh) (1) t w(sckl) (1) sck high and low time master mode, f pclk = 36 mhz, presc = 4 50 60 t su(mi) (1) t su(si) (1) data input setup time master mode 5 slave mode 5 t h(mi) (1) data input hold time master mode 5 t h(si) (1) slave mode 4 t a(so) (1)(2) 2. min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. data output access time slave mode, f pclk = 20 mhz 0 3t pclk t dis(so) (1)(3) 3. min time is for the minimum time to invalidate the ou tput and the max time is for the maximum time to put the data in hi-z data output disable time slave mode 2 10 t v(so) (1) data output valid time slave mode (after enable edge) 25 t v(mo) (1) data output valid time master mode (after enable edge) 5 t h(so) (1) data output hold time slave mode (after enable edge) 15 t h(mo) (1) master mode (after enable edge) 2 docid15056 rev 5 63/80 stm32f102x8, stm32f102xb electrical characteristics 79 figure 27. spi timing diagram - slave mode and cpha=0 figure 28. spi timing diagra m - slave mode and cpha=1 (1) 1. measurement points are done at cmos levels: 0.3v dd and 0.7v dd. ai14134c sck input cpha= 0 mosi input miso out p ut cpha= 0 ms b o u t msb in bi t6 ou t lsb in lsb out cpol=0 cpol=1 bit1 in nss input t su(nss) t c(sck) t h(nss) t a(so) t w(sckh) t w(sckl) t v(so) t h(so) t r(sck) t f(sck) t dis(so) t su(si) t h(si) ai14135 sck input cpha=1 mosi input miso out p ut cpha=1 ms b o u t msb in bi t6 ou t lsb in lsb out cpol=0 cpol=1 bit1 in t su(nss) t c(sck) t h(nss) t a(so) t w(sclh) t w(scll) t v(so) t h(so) t r(scl) t f(scl) t dis(so) t su(si) t h(si) nss input electrical characteristics stm32f102x8, stm32f102xb 64/80 docid15056 rev 5 figure 29. spi timing diagram - master mode (1) 1. measurement points are done at cmos levels: 0.3v dd and 0.7v dd. usb characteristics the usb interface is usb- if certified (full speed). table 42. usb startup time symbol parameter max unit t startup usb transceiver startup time 1 s ai14136v2 sck output cpha= 0 mosi outut miso inp ut cpha= 0 ms bin m sb out bi t6 in lsb out lsb in cpol=0 cpol=1 b i t1 out nss input t c(sck) t w(sckh) t w(sckl) t r(sck) t f(sck) t h(mi) high sck output cpha=1 cpha=1 cpol=0 cpol=1 t su(mi) t v(mo) t h(mo) docid15056 rev 5 65/80 stm32f102x8, stm32f102xb electrical characteristics 79 figure 30. usb timings: definition of data signal rise and fall time 5.3.17 12-bit adc characteristics unless otherwise specified, the parameters given in table 47 are derived from tests performed under ambient temperature, f pclk2 frequency and v dda supply voltage conditions su mmarized in table 8 . note: it is recommended to perform a calibration after each power-up. table 43. usb dc electrical characteristics symbol parameter conditions min. (1) 1. all the voltages are measured from the local ground potential. max. (1) unit input levels v dd usb operating voltage (2) 2. to be compliant with the usb 2.0 full-speed electrical specification, the usb_dp (d+) pin should be pulled up with a 1.5 k resistor to a 3.0-to-3.6 v voltage range. 3.0 (3) 3. the stm32f102xx usb functionality is ensured dow n to 2.7 v but not the full usb electrical characteristics which are degraded in the 2.7-to-3.0 v v dd voltage range. 3.6 v v di (4) 4. guaranteed by design, not tested in production. differential input sensitivity i(usb_dp, usb_dm) 0.2 v v cm (4) differential common mode range includes v di range 0.8 2.5 v se (4) single ended receiver threshold 1.3 2.0 output levels v ol static output level low r l of 1.5 k to 3.6 v (5) 5. r l is the load connected on the usb drivers 0.3 v v oh static output level high r l of 15 k to v ss (5) 2.8 3.6 table 44. usb: full speed electrical characteristics of the driver (1) 1. guaranteed by design, not tested in production. symbol parameter conditions min max unit t r rise time (2) 2. measured from 10% to 90% of the data signal. for more detailed informations, please refer to usb specification - chapter 7 (version 2.0). c l = 50 pf 420ns t f fall time (2) c l = 50 pf 4 20 ns t rfm rise/ fall time matching t r /t f 90 110 % v crs output signal cro ssover voltage 1.3 2.0 v ai14137 t f differen tial data l ines v ss v cr s t r crossover points electrical characteristics stm32f102x8, stm32f102xb 66/80 docid15056 rev 5 equation 1: r ain max formula: the formula above ( equation 1 ) is used to determine the maximum external impedance allowed for an error below 1/4 of lsb. here n = 12 (from 12-bit resolution). table 45. adc characteristics symbol parameter conditions min typ max unit v dda power supply 2.4 3.6 v f adc adc clock frequency 0.6 12 mhz f s (1) 1. guaranteed by design, not tested in production. sampling rate 0.05 0.85 msps f trig (1) external trigger frequency f adc = 12 mhz 823 khz 17 1/f adc v ain conversion voltage range (2) 2. vref+ is internally connected to vdda and vref- is internally connected to vssa, 0 (v ssa or v ref- tied to ground) v ref+ v r ain (1) external input impedance see equation 1 and table 48 for details 50 ? r adc (1) sampling switch resistance 1 ? c adc (1) internal sample and hold capacitor 8pf t cal (1) calibration time f adc = 12 mhz 5.9 s 83 1/f adc t lat (1) injection trigger conversion latency f adc = 12 mhz 0.214 s 3 (3) 3. for external triggers, a delay of 1/f pclk2 must be added to the latency specified in table 47 . 1/f adc t latr (1) regular trigger conversion latency f adc = 12 mhz 0.143 s 2 (3) 1/f adc t s (1) sampling time f adc = 12 mhz 0.125 19.95 s 1.5 239.5 1/f adc t stab (1) power-up time 0 0 1 s t conv (1) total conversion time (including sampling time) f adc = 12 mhz 1.2 21 s 14 to 252 (t s for sampling +12.5 for successive approximation) 1/f adc r ain t s f adc c adc 2 n2 + () ln ------------------------------------------------------------- r adc ? < docid15056 rev 5 67/80 stm32f102x8, stm32f102xb electrical characteristics 79 table 46. r ain max for f adc = 12 mhz (1) 1. data guaranteed by design, not tested in production. t s (cycles) t s (s) r ain max (k ) 1.5 0.13 0.4 7.5 0.63 5.9 13.5 1.13 11.4 28.5 2.38 25.2 41.5 3.46 37.2 55.5 4.63 50 71.5 5.96 na 239.5 19.96 na table 47. adc accuracy - limited test conditions (1) 1. adc dc accuracy values are measured after internal calibration. symbol parameter test conditions typ max (2) 2. based on characterization, not tested in production. unit et total unadjusted error f pclk2 = 48 mhz, f adc = 12 mhz, r ain < 10 k , v dda = 3 v to 3.6 v t a = 25 c measurements made after adc calibration 1.3 2 lsb eo offset error 1 1.5 eg gain error 0.5 1.5 ed differential linearity error 0.7 1 el integral linearity error 0.8 1.5 table 48. adc accuracy (1) (2) (3) 1. adc dc accuracy values are measured after internal calibration. 2. better performance could be achieved in restricted v dd , frequency and temperature ranges. 3. adc accuracy vs. negative injection current: inject ing a negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conv ersion being performed on another analog input. it is recommended to add a schottky diode (pin to ground) to analog pins which may potentially inject negative currents. any positive injection current within the limits specified for i inj(pin) and i inj(pin) in section 5.3.13 does not affect the adc accuracy. symbol parameter test conditions typ max (4) 4. based on characterization, not tested in production. unit et total unadjusted error f pclk2 = 48 mhz, f adc = 12 mhz, r ain < 10 k , v dda = 2.4 v to 3.6 v measurements made after adc calibration 2 5 lsb eo offset error 1.5 2.5 eg gain error 1.5 3 ed differential linearity error 1 2 el integral linearity error 1.5 3 electrical characteristics stm32f102x8, stm32f102xb 68/80 docid15056 rev 5 figure 31. adc accuracy characteristics figure 32. typical connecti on diagram using the adc 1. refer to table 47 for the values of r ain , r adc and c adc . 2. c parasitic represents the capacitance of the pcb (dependent on soldering and pcb layout quality) plus the pad capacitance (roughly 7 pf). a high c parasitic value will downgrade conversion accuracy. to remedy this, f adc should be reduced. e o e g 1lsb ideal (1) example of an actual transfer curve (2) the ideal transfer curve (3) end point correlation line e t =total u nadjusted er ror: maximum deviation between the actual and the ideal transfer curves. e o =offset error: deviation between the first actual transition and the first ideal one. e g =gain er ror: deviation between the last ideal transition and the last actual one. e d =differential linearity error: maximum deviation between actual steps and the ideal one. e l =integral linearity error: maximum deviation between any actual transition and the end point correlation line. 4095 4094 4093 5 4 3 2 1 0 7 6 1234567 4093 4094 4095 4096 (1) (2) e t e d e l (3) v dda v ssa ai15497 v dda 4096 [1lsb ideal = ai14974b stm32f102 v dd ainx i l 1 a 0.6 v v t r ain (1) c parasitic v ain 0.6 v v t r adc (1) 12-bit converter c adc (1) sample and hold adc converter docid15056 rev 5 69/80 stm32f102x8, stm32f102xb electrical characteristics 79 general pcb design guidelines power supply decoupling should be performed as shown in figure 33 . the 10 nf capacitors should be ceramic (good quality). they should be placed as close as possible to the chip. figure 33. power supply and reference decoupling 5.3.18 temperature sensor characteristics v dda stm32f102xx 1 f // 10 nf v ssa ai14980b table 49. ts characteristics symbol parameter min typ max unit t l (1) 1. guaranteed by characterizati on, not tested in production. v sense linearity with temperature 1.5 c avg_slope (1) average slope 4.35 mv/c v 25 (1) voltage at 25c 1.42 v t start (2) 2. data guaranteed by design, not tested in production. startup time 4 10 s t s_temp (3)(2) 3. shortest sampling time can be determined in the application by multiple iterations. adc sampling time when reading the temperature 17.1 s package characteristics stm32f102x8, stm32f102xb 70/80 docid15056 rev 5 6 package characteristics 6.1 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions a nd product status are available at: www.st.com . ecopack ? is an st trademark. figure 34. lqfp64 ? 10 x 10 mm, 48-pin low-profile quad flat package outline 1. drawing is not to scale. 2. dimensions are in millimeters. a1 a2 a seating plane ccc c b c c a1 l l1 k gauge plane 0.25 mm identification pin 1 d d1 d3 e 1 16 17 32 33 48 49 64 e3 e1 e 5w_me_v2 docid15056 rev 5 71/80 stm32f102x8, stm32f102xb package characteristics 79 figure 35. lqfp64 recommended footprint dimensions (1)(2) 1. drawing is not to scale. 2. dimensions are in millimeters. table 50. lqfp64 ? 10 x 10 mm, 64-pin low- profile quad flat package mechanical data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. min typ max min typ max a 1.600 0.0630 a1 0.050 0.150 0.0020 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 0.200 0.0035 0.0079 d 11.800 12.000 12.200 0.4646 0.4724 0.4803 d1 9.800 10.000 10.200 0.3858 0.3937 0.4016 d3 7.50 0.2953 e 11.800 12.000 12.200 0.4646 0.4724 0.4803 e1 9.800 10.000 10.200 0.3858 0.3937 0.4016 e3 7.500 0.2953 e 0.500 0.0197 l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 1.00 0.0394 ccc 0.080 0.0031 k 03.57 03.57 48 32 49 64 17 1 16 1.2 0.3 33 10.3 12.7 10.3 0.5 7.8 12.7 ai14909 package characteristics stm32f102x8, stm32f102xb 72/80 docid15056 rev 5 figure 36. lqfp48 ? 7 x 7 mm, 48-pin low-profile quad flat package outline 1. drawing is not to scale. 2. dimensions are in millimeters. 5b_me_v2 pin 1 identification ccc c c d3 0.25 mm gauge plane b a1 a a2 c a1 l1 l d d1 e3 e1 e e 12 1 13 24 25 36 37 48 seating plane k docid15056 rev 5 73/80 stm32f102x8, stm32f102xb package characteristics 79 figure 37. lqfp48 recommended footprint dimensions (1)(2) 1. drawing is not to scale. 2. dimensions are in millimeters. table 51. lqfp48 ? 7 x 7 mm, 48-pin low-profile quad flat package mechanical data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. min typ max min typ max a 1.600 0.0630 a1 0.050 0.150 0.0020 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 0.200 0.0035 0.0079 d 8.800 9.000 9.200 0.3465 0.3543 0.3622 d1 6.800 7.000 7.200 0.2677 0.2756 0.2835 d3 5.500 0.2165 e 8.800 9.000 9.200 0.3465 0.3543 0.3622 e1 6.800 7.000 7.200 0.2677 0.2756 0.2835 e3 5.500 0.2165 e 0.500 0.0197 l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 1.000 0.0394 ccc 0.080 0.0031 k 03.57 03.57 9.70 5.80 7.30 12 24 0.20 7.30 1 37 36 1.20 5.80 9.70 0.30 25 1.20 0.50 ai14911b 13 48 package characteristics stm32f102x8, stm32f102xb 74/80 docid15056 rev 5 6.2 thermal characteristics the maximum chip junction temperature (t j max) must never exceed the values given in table 8: general operating conditions on page 30 . the maximum chip-junction temperature, t j max, in degrees celsius, may be calculated using the following equation: t j max = t a max + (p d max ja ) where: ? t a max is the maximum ambient temperature in c, ? ja is the package junction-to-ambient thermal resistance, in c/w, ? p d max is the sum of p int max and p i/o max (p d max = p int max + p i/o max), ? p int max is the product of i dd and v dd , expressed in watts. th is is the maximum chip internal power. p i/o max represents the maximum power dissipation on output pins where: p i/o max = (v ol i ol ) + ((v dd ? v oh ) i oh ), taking into account the actual v ol / i ol and v oh / i oh of the i/os at low and high level in the application. 6.3 reference document jesd51-2 integrated circuits thermal test method environment conditions - natural convection (still air). available from www.jedec.org. table 52. package thermal characteristics symbol parameter value unit ja thermal resistance junction-ambient lqfp48 - 7 7 mm / 0.5 mm pitch 55 c/w thermal resistance junction-ambient lqfp64 - 10 10 mm / 0.5 mm pitch 45 docid15056 rev 5 75/80 stm32f102x8, stm32f102xb package characteristics 79 6.3.1 evaluating the maximum juncti on temperature for an application when ordering the microcontroller, the temperature range is specified in the ordering information scheme shown in table 55: ordering information scheme . each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to a specific ma ximum junction temperature. here, only temperature range 6 is available (?40 to 85 c). the following example shows how to calculate the temperature range needed for a given application, making it possible to check wh ether the required temperature range is compatible with the stm32f102xx junction temperature range. example: high-performance application assuming the following ap plication conditions: maximum ambient temperature t amax = 82 c (measured according to jesd51-2), i ddmax = 50 ma, v dd = 3.5 v, maximum 20 i/os used at the same time in output at low level with i ol = 8 ma, v ol = 0.4 v and maximum 8 i/os used at the same time in output mode at low level with i ol = 20 ma, v ol = 1.3 v p intmax = 50 ma 3.5 v= 175 mw p iomax = 20 8 ma 0.4 v + 8 20 ma 1.3 v = 272 mw this gives: p intmax = 175 mw and p iomax = 272 mw p dmax = 175 + 272 = 447 mw thus: p dmax = 447 mw using the values obtained in table 54 t jmax is calculated as follows: ? for lqfp64, 45 c/w t jmax = 82 c + (45 c/w 447 mw) = 82 c + 20.1 c = 102.1 c this is within the junction temperature range of the stm32f102xx (?40 < t j < 105 c). figure 38. lqfp64 p d max vs. t a 0 100 200 300 400 500 600 700 65 75 85 95 105 115 t a (c) p d (mw) suffix 6 ordering information scheme stm32f102x8, stm32f102xb 76/80 docid15056 rev 5 7 ordering information scheme table 53. ordering information scheme example: stm32 f 102 c 8 t 6 xxx device family stm32 = arm-based 32-bit microcontroller product type f = general-purpose device subfamily 102 = usb access line, usb 2.0 full-speed interface pin count c = 48 pins r = 64 pins flash memory size 8 = 64 kbytes of flash memory b = 128 kbytes of flash memory package t = lqfp temperature range 6 = industrial temperature range, ?40 to 85 c. options xxx = programmed parts tr = tape and real docid15056 rev 5 77/80 stm32f102x8, stm32f102xb revision history 79 8 revision history table 54. document revision history date revision changes 23-sep-2008 1 initial release. 23-apr-2009 2 i/o information clarified on page 1 . figure 1: stm32f102t8 medium- density usb access line block diagram and figure 5: memory map modified. in table 4: medium-density stm32f102xx pin definitions : pb4, pb13, pb14, pb15, pb3/traceswo moved from default column to remap column. p d value added for lqfp64 package in table 8: general operating conditions . note modified in table 13: maximum current consumption in run mode, code with data processing running from flash and table 15: maximum current consumption in sleep mode, code running from flash or ram . figure 13 , figure 14 and figure 15 show typical curves. figure 31: adc accuracy characteristics modified. figure 33: power supply and reference decoupling modified. table 20: high-speed external user clock characteristics and ta ble 21 : low-speed external user clock characteristics modified. acc hsi max values modified in table 24: hsi oscillator characteristics . small text changes. 22-sep-2009 3 note 5. updated in table 4: medium-density stm32f102xx pin definitions . v rerint and t coeff added to table 12: embedded internal reference voltage . typical i dd_vbat value added in table 16: typical and maximum current consumptions in stop and standby modes . figure 12: typical current consumption on vbat with rtc on versus temperature at different vbat values added. f hse_ext min modified in table 20: high-speed external user clock characteristics . c l1 and c l2 replaced by c in table 22: hse 4-16 mhz oscillator characteristics and table 23: lse oscillator characteristics (flse = 32.768 khz) , notes modified and moved below the tables. table 24: hsi oscillator characteristics modified. conditions removed from table 26: low-power mode wakeup timings . note 1. modified below figure 18: typical application with an 8 mhz crystal . figure 25: recommended nrst pin protection modified. iec 1000 standard updated to iec 61000 and sae j1752/3 updated to iec 61967-2 in section 5.3.10: emc characteristics on page 48 . jitter added to table 27: pll characteristics . table 43: spi characteristics modified. c adc and r ain parameters modified in table 47: adc characteristics . r ain max values modified in table 48: rain max for fadc = 12 mhz . small text changes. revision history stm32f102x8, stm32f102xb 78/80 docid15056 rev 5 27-sep-2012 4 figure 2: clock tree : added flitfclk and note 3. , and modified note 1. . updated note 2. in table 41: i2c characteristics . updated figure 25: recommended nrst pin protection . changed t w(sckh) to tw(sclh ), t w(sckl) to t w(scll) , t r(sck) to t r(scl) , t f(sck ) to t f(scl) , and t su(sta:sto) to t w(sto:sta) in figure 26: i2c bus ac waveforms and measurement circuit(1) . changed note for i lkg and r pu and updated note 1. content in table 36: i/o static characteristics . updated text related to cmos and ttl compliance and added figure 20 , figure 21 , figure 22 , and figure 23 . updated section : output driving current . in table 43: spi characteristics , removed note 1 related to spi1 remapped characteristics. added ducy (hsi) in table 24: hsi oscillator characteristics . table 23: lse oscillator characteristics (flse = 32.768 khz) : removed note 2 related to oscillator selection, updated note 2. , and t su(lse ) specified for various ambient temperature values. updated note 2. and note 3. below figure 35: recommended footprint (dimensions in mm) (1)(2)(3) . table 37: output voltage characteristics : updated v ol and v oh conditions for ttl and cmos outputs and added note 2. . replaced ?tbd? by ?-? for ?max? specification of ?supply current in standby mode? in table 16: typical and maximum current consumptions in stop and standby modes . removed ?except for analog inputs? from paragraph ?gpios (general- purpose inputs/outputs) in chapter 2.3: overview . updated t w(hse) min value in table 20: high-speed external user clock characteristics . added note 2. in table 5: voltage characteristics . updated note 3. , note 4. and note 5. in table 6: current characteristics . updated note 1. in table 38: i/o ac characteristics . added chapter 5.3.12: i/o current injection characteristics . updated note 2. in table 41: i2c characteristics . updated ?output driving current? paragraph in chapter 5.3.13: i/o port characteristics . removed note 4 and updated note 3. in table 41: i2c characteristics . updated figure 29: spi timing diagram - master mode(1) (sck output instead of input). replaced every occurrence of usbdp or usbdm by usb_dp or usb_dm, respectively. table 54. document revision history (continued) date revision changes docid15056 rev 5 79/80 stm32f102x8, stm32f102xb revision history 79 02-aug-2013 5 removed sentence in ?unless otherwise specified the parameters ...? in i2c interface characteristics section. added v in in table 8: general operating conditions added note 5. in table 23: hsi oscillator characteristics modified charge device model in table 33: esd absolute maximum ratings updated ?v il ? and ?v ih ? in table 34: i/o static characteristics added notes to figure 20: standard i/o input characteristics - cmos port , figure 21: standard i/o input characteristics - ttl port , figure 22: 5 v tolerant i/o input characteristics - cmos port and figure 23: 5 v tolerant i/o input characteristics - ttl port updated figure 24: i/o ac characteristics definition updated note 2. and 3. in table 39: i2c characteristics updated figure 26: i2c bus ac waveforms and measurement circuit(1) updated title of table 40: scl frequency (fpclk1= 36 mhz, vdd_i2c = 3.3 v) updated table 47: adc characteristics updated section 6.1: package mechanical data table 54. document revision history (continued) date revision changes stm32f102x8, stm32f102xb 80/80 docid15056 rev 5 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, 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